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公开(公告)号：US20080091961A1
公开(公告)日：2008-04-17
申请号：US11949129
申请日：2007-12-03
申请人： Hayden Cranford , Louis Hsu , James Mason
发明人： Hayden Cranford , Louis Hsu , James Mason
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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32.发明申请公开(公告)号：US20070096720A1
公开(公告)日：2007-05-03
申请号：US11262101
申请日：2005-10-28
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.
摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。
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33.发明申请STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效在模拟电路中局部地提供闸门泄漏隔离的结构和方法公开(公告)号：US20070075789A1
公开(公告)日：2007-04-05
申请号：US11163013
申请日：2005-09-30
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03L7/0891
摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.
摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。
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公开(公告)号：US20070075731A1
公开(公告)日：2007-04-05
申请号：US11163015
申请日：2005-09-30
IPC分类号： H03K19/003
CPC分类号： H03K19/00346
摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.
摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。
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公开(公告)号：US20060192611A1
公开(公告)日：2006-08-31
申请号：US10906628
申请日：2005-02-28
申请人： Anthony Bonaccio , Hayden Cranford
发明人： Anthony Bonaccio , Hayden Cranford
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.
摘要翻译： 公开了一种体偏置增强电流镜参考电路，其中电流镜装置的体偏置电压被改变以调节其阈值电压。 复制镜晶体管的漏极和体电位都被控制为选定值。 漏极设置为NFET电流镜器件的预期直流电压输出。 身体电位被设置为最大期望值，以防止由反馈控制电路实现的一个或多个电流镜装置的体对扩散结的正向偏置。 低频，低精度运算放大器驱动复制负载装置的栅极，使得复制NFET电流镜装置的主体被设置为最大偏置电压。 最大偏置电压也用于偏置二极管连接的NMOS参考晶体管的主体，使得NFET电流镜器件中的电流将近似等于连接二极管的NMOS参考电流。 辅助NFET电流镜装置可以被添加到主体偏置的增强电流镜电路中，其中主体连接到地面，如在未修改的电流镜中，以消除电流输出的非单调性。
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公开(公告)号：US20060056128A1
公开(公告)日：2006-03-16
申请号：US10940543
申请日：2004-09-14
申请人： Hayden Cranford , Louis Hsu , James Mason
发明人： Hayden Cranford , Louis Hsu , James Mason
IPC分类号： H01H59/00
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
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公开(公告)号：US20050233478A1
公开(公告)日：2005-10-20
申请号：US10709109
申请日：2004-04-14
IPC分类号： H01L21/00 , H01L23/525 , H01L27/08 , H01P3/08
CPC分类号： H01L27/0802 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.
摘要翻译： 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。
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38.发明申请公开(公告)号：US20050058231A1
公开(公告)日：2005-03-17
申请号：US10665235
申请日：2003-09-17
申请人： Hayden Cranford , Westerfield Ficken , Wentai Liu
发明人： Hayden Cranford , Westerfield Ficken , Wentai Liu
CPC分类号： H04L25/03133
摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.
摘要翻译： 公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。 本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。
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公开(公告)号：US20050046489A1
公开(公告)日：2005-03-03
申请号：US10650396
申请日：2003-08-28
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Todd Rasmus , Peter Seidel
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
摘要翻译： 公开了一种用于锁相环的自适应电压调节器。 锁相环包括相位检测器，电荷泵，低通滤波器和压控振荡器，其中低通滤波器将控制电压输入到压控振荡器以产生输出时钟。 根据本文公开的方法和系统，自适应电压调节器耦合到低通滤波器的输出，用于在锁相环的正常操作期间感测控制电压，并且用于动态调整供电电压，即 响应于控制电压输入到压控振荡器，使得锁相环将控制电压保持在参考电压的预定范围内。
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