公开(公告)号：US07338555B2

公开(公告)日：2008-03-04

申请号：US10937344

申请日：2004-09-10

申请人： Hiroyuki Fukuyama ,  Wataru Nakao ,  Shinya Kusunoki ,  Kazuya Takada ,  Akira Hakomori

发明人： Hiroyuki Fukuyama ,  Wataru Nakao ,  Shinya Kusunoki ,  Kazuya Takada ,  Akira Hakomori

IPC分类号： C30B25/00

CPC分类号： C23C8/28 ,  C23C8/24 ,  C30B29/20 ,  C30B29/38 ,  C30B33/00

摘要： A highly crystalline aluminum nitride multi-layered substrate comprising a single-crystal α-alumina substrate, an aluminum oxynitride layer and a highly crystalline aluminum nitride film as the outermost layer which are formed in the mentioned order, wherein the aluminum oxynitride layer has a threading dislocation density of 6.3×107/cm2 or less and a crystal orientation expressed by the half-value width of its rocking curve of 4,320 arcsec or less; and a production process thereof.

摘要翻译： 包含按照上述顺序形成的单晶α-氧化铝基板，氮氧化铝层和高结晶氮化铝膜作为最外层的高结晶氮化铝多层基板，其中，氮氧化铝层具有螺纹 位错密度为6.3×10 7 / cm 2以下，由其摇摆曲线的半值宽度表示的晶体取向为4,320arcsec以下; 及其制造方法。

公开(公告)号：US20070208966A1

公开(公告)日：2007-09-06

申请号：US11709786

申请日：2007-02-23

申请人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

发明人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC分类号： G06K5/04

CPC分类号： G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

摘要： A semiconductor test circuit includes an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives a serial data including a command code and a control data. The controller receives a control signal and outputs an internal control signal based on the control signal. The setting circuit receives the serial data and outputs it in response to the internal control signal. The command generator generates an interface signal based on the serial data received from the setting circuit. The switching circuit has ports, receives the signal from one of the ports and outputs the received signal to another one of the ports in response to the internal control signal and the command code. The comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

摘要翻译： 半导体测试电路包括输入端子，控制器，设置电路，命令发生器，传输路径切换电路和比较器。 输入端子接收包括命令码和控制数据的串行数据。 控制器接收控制信号，并根据控制信号输出内部控制信号。 设置电路接收串行数据并根据内部控制信号输出。 命令发生器基于从设置电路接收的串行数据生成接口信号。 开关电路具有端口，从一个端口接收信号，并响应于内部控制信号和命令码将接收的信号输出到另一个端口。 比较器将从命令发生器接收的接口信号与从开关电路接收的信号进行比较。

公开(公告)号：US07220314B2

公开(公告)日：2007-05-22

申请号：US10809398

申请日：2004-03-26

申请人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

发明人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

IPC分类号： C30B25/00

CPC分类号： H01L33/32 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02658

摘要： A single crystalline aluminum nitride laminated substrate comprising a single crystalline α-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less.The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide.The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.

摘要翻译： 包括单晶α-Al 2 O 3 N 3衬底的单晶氮化铝层压衬底，例如蓝宝石衬底，形成在衬底上的氧氮化铝层和单晶 氮化铝膜作为最外层，其中单晶氮化铝中的位错密度为10 8 / cm 2以下。 上述单晶氮化铝层压基板是通过在碳，氮和一氧化碳的存在下加热氮化基板而形成的。 上述单晶氮化铝膜具有定位密度，晶格不匹配和结晶度极好的特点。 可以在该氮化铝膜上形成具有优异发光效率的III族元素氮化物膜。 上述层叠基板用于III族元素氮化物膜的基底基板，发光元件和弹性表面波元件。

公开(公告)号：US20050059257A1

公开(公告)日：2005-03-17

申请号：US10937344

申请日：2004-09-10

申请人： Hiroyuki Fukuyama ,  Wataru Nakao ,  Shinya Kusunoki ,  Kazuya Takada ,  Akira Hakomori

发明人： Hiroyuki Fukuyama ,  Wataru Nakao ,  Shinya Kusunoki ,  Kazuya Takada ,  Akira Hakomori

IPC分类号： C23C8/24 ,  C23C8/28 ,  C23C28/04 ,  C30B29/20 ,  C30B29/38 ,  C30B33/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/84

CPC分类号： C23C8/28 ,  C23C8/24 ,  C30B29/20 ,  C30B29/38 ,  C30B33/00

摘要： A highly crystalline aluminum nitride multi-layered substrate comprising a single-crystal α-alumina substrate, an aluminum oxynitride layer and a highly crystalline aluminum nitride film as the outermost layer which are formed in the mentioned order, wherein the aluminum oxynitride layer has a threading dislocation density of 6.3×107/cm2 or less and a crystal orientation expressed by the half-value width of its rocking curve of 4,320 arcsec or less; and a production process thereof.

摘要翻译： 包含按照上述顺序形成的单晶α-氧化铝基板，氮氧化铝层和高结晶氮化铝膜作为最外层的高结晶氮化铝多层基板，其中，氮氧化铝层具有螺纹 位错密度为6.3×10 7 / cm 2以下，由其摇摆曲线的半值宽度表示的晶体取向为4,320arcsec以下; 及其制造方法。

公开(公告)号：US06744076B2

公开(公告)日：2004-06-01

申请号：US10247539

申请日：2002-09-20

申请人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

发明人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

IPC分类号： H01L2106

CPC分类号： H01L33/32 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02658

摘要： A single crystalline aluminum nitride laminated substrate comprising a single crystalline &agr;-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less. The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide. The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.

摘要翻译： 包括单晶Al-Al 2 O 3衬底（例如蓝宝石衬底），形成在衬底上的氧氮化铝层和单晶氮化铝膜作为最外层的单晶氮化铝层压衬底，其中单晶铝中的位错密度 氮化物为10 8 / cm 2以下。上述单晶氮化铝层叠基板通过在碳，氮和一氧化碳的存在下加热氮化基板而形成。上述单晶氮化铝膜具有 法位错密度小，晶格不匹配，结晶性好。 可以在该氮化铝膜上形成具有优异发光效率的III族元素氮化物膜。 上述层叠基板用于III族元素氮化物膜的基底基板，发光元件和弹性表面波元件。

公开(公告)号：US06510097B2

公开(公告)日：2003-01-21

申请号：US09985237

申请日：2001-11-02

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： G11C800

CPC分类号： G11C11/4085 ,  G11C7/1021 ,  G11C7/1042 ,  G11C8/00 ,  G11C8/12

摘要： An interface circuit controls access to a dynamic random-access memory having multiple banks, each bank having multiple rows of memory cells, according to received address signals. The address signals are decoded in such a way that when access to a consecutive series of addresses crosses from a first row to a second row, these two rows are always disposed in separate banks. The second row is activated during access to the first row, and the first row is precharged during access to the second row, enabling access to proceed without interruption across the row boundary. In particular, burst access can proceed from row to row continuously.

摘要翻译： 根据接收到的地址信号，接口电路控制对具有多个存储体的动态随机存取存储器的访问，每个存储体具有多行存储器单元。 地址信号以这样一种方式进行解码，即当对连续的一系列地址的访问从第一行到第二行交叉时，这两行总是被布置在单独的存储体中。 第二行在访问第一行期间被激活，并且第一行在访问第二行期间被预充电，使得访问能够在行边界上不间断地进行。 特别地，突发访问可以从一行到另一行继续进行。

公开(公告)号：US6025740A

公开(公告)日：2000-02-15

申请号：US115662

申请日：1993-09-03

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： H01L21/82 ,  G06F1/10 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00323

摘要： A clock feeding circuit for an integrated circuit includes logic circuit regions, a clock signal source, an input buffer connected to the source, and delay adjusting circuits. Each logic circuit region has a plurality of logic circuits, a buffer circuit for receiving the clock signal and providing it to the logic circuits, and interconnections wiring the logic circuits to the buffer circuit such that clock skew is minimized in the region. The adjusting circuits are disposed between the buffer and the respective logic circuit regions. Each adjusting circuit is composed of a plurality of delay elements, the number of which is pre-selected to determine the delay of the clock signal passing through it. A method for designing the integrated circuit includes (a) creating a schematic representation of the integrated circuit, (b) determining a layout and interconnections of each region, by which the clock skew in the regions is minimized among the logic circuits of each region, including simulating transmission of a clock signal from the clock source to each region to determine delays times of the clock signal from the clock source to the logic circuits; and (c) determining adjustments to the delay circuits which provide a minimum difference among time delays for the clock signal to reach one logic circuit in each region.

摘要翻译： 用于集成电路的时钟馈电电路包括逻辑电路区域，时钟信号源，连接到源极的输入缓冲器和延迟调整电路。 每个逻辑电路区域具有多个逻辑电路，用于接收时钟信号并将其提供给逻辑电路的缓冲电路，以及将逻辑电路连接到缓冲电路的互连，使得该区域中的时钟偏移最小化。 调整电路设置在缓冲器和各个逻辑电路区域之间。 每个调整电路由多个延迟元件组成，其数量被预先选择以确定通过它的时钟信号的延迟。 一种用于设计集成电路的方法包括（a）创建集成电路的示意图，（b）确定每个区域的布局和互连，通过该布局和互连，区域中的时钟偏移在每个区域的逻辑电路中最小化， 包括模拟从时钟源到每个区域的时钟信号的传输，以确定从时钟源到逻辑电路的时钟信号的延迟时间; 和（c）确定对延迟电路的调整，所述延迟电路在时钟信号的时间延迟之间提供最小差异以到达每个区域中的一个逻辑电路。