公开(公告)号：US06830948B2

公开(公告)日：2004-12-14

申请号：US10168629

申请日：2002-09-26

申请人： Masayoshi Koike ,  Akira Kojima ,  Toshio Hiramatsu ,  Yuta Tezen

发明人： Masayoshi Koike ,  Akira Kojima ,  Toshio Hiramatsu ,  Yuta Tezen

IPC分类号： H01L2106

CPC分类号： H01L33/0075 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/007 ,  H01S5/32341 ,  H01S2304/12

摘要： By using a mask 4, a first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, striped-shaped, or grid-like structure, so as to provide a trench/post. Thus, without removing the mask 4 formed on a top surface of the upper layer of the post, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, with a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. The second Group III nitride compound layer 32 does not grow epitaxially on the mask 4. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth and a region having less threading dislocations can be formed in the buried portion of the trench.

摘要翻译： 通过使用掩模4，蚀刻第一III族氮化物化合物半导体层31，从而形成诸如点状，条状或栅格状结构的岛状结构，从而提供沟槽/ 帖子 因此，在不去除形成在柱的上层的顶表面上的掩模4的情况下，第二III族氮化物化合物层32可以垂直和侧向地外延生长，其中沟槽的侧壁/侧壁用作核， 从而埋入沟槽并且还在垂直方向上生长该层。 第二III族氮化物化合物层32不会在掩模4上外延生长。在这种情况下，可以在第二III族氮化物化合物的上部防止包含在第一III族氮化物化合物半导体层31中的穿透位错的传播 通过横向外延生长形成的半导体32和具有较少穿透位错的区域可以形成在沟槽的掩埋部分中。

公开(公告)号：US06815244B2

公开(公告)日：2004-11-09

申请号：US10608620

申请日：2003-06-27

申请人： Harald Böttner ,  Axel Schubert ,  Joachim Nurnus ,  Christa Künzel

发明人： Harald Böttner ,  Axel Schubert ,  Joachim Nurnus ,  Christa Künzel

IPC分类号： H01L2106

CPC分类号： H01L35/34 ,  H01L35/16

摘要： A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive V-VI layer, in particular a (Bi, Sb)2 (Te, Se)3 layer. The V-VI layer is formed by use of a seed layer or by a structure formed in the substrate, and disposed relative to the substrate such that an angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. The orientation can also be effected by an electric field. Components are formed of the thermoelectric layer structure in which the angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. As a result, the known anisotropy of the V-VI materials can advantageously be used for the construction of components.

公开(公告)号：US06784018B2

公开(公告)日：2004-08-31

申请号：US09943187

申请日：2001-08-29

申请人： Kristy A. Campbell ,  John T. Moore

发明人： Kristy A. Campbell ,  John T. Moore

IPC分类号： H01L2106

CPC分类号： H01L45/1233 ,  H01L45/04 ,  H01L45/085 ,  H01L45/143 ,  H01L45/1616 ,  H01L45/1658 ,  H01L45/1683

摘要： A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.

摘要翻译： 在基板上形成第一导电电极材料。 在其上形成包含硫属元素的材料。 硫族化物材料包括AxSey。 在硫族化物材料上形成含银层。 银被照射有效地破坏硫族化物材料在含银层和硫族化物材料的界面处的硫属化物键，并将至少一些银扩散到硫族化物材料中。 在照射之后，硫族化物材料外表面暴露于含有碘的流体，其有效地减少硫族化物材料外表面的暴露之前的粗糙度。 曝光后，将第二导电电极材料沉积在硫族化物材料上，并且至少在硫族化物材料上连续并完全覆盖，并且将第二导电电极材料形成为器件的电极。

公开(公告)号：US06537846B2

公开(公告)日：2003-03-25

申请号：US09823550

申请日：2001-03-30

申请人： Heon Lee ,  Chung Ching Yang

发明人： Heon Lee ,  Chung Ching Yang

IPC分类号： H01L2106

CPC分类号： H01L21/2007 ,  H01L21/76251

摘要： A selenidation reaction for bonding one or more active substrates to a base substrate is disclosed. A bonded-substrate is fabricated by forming a first multi-stacked layer of selenium and indium on a bonding surface of an active substrate and forming a second multi-stacked layer of selenium and indium on a mounting surface of a base substrate. The first and second multi-stacked layers are placed into contact with each other with substantially no pressure. Then the active substrate and the base substrate are bonded to each other by annealing them in an inert ambient to form an indium-selenium compound bond layer that adhesively bonds the substrates to each other. The annealing can occur at a lower temperature than prior wafer-bonding processes and the first and second multi-stacked layers can be deposited over a wide range of relatively low temperatures including room temperature. Additionally, tellurium can be added to the selenium of either one or both of the first and second multi-stacked layers to reduce the annealing temperature and to form an indium-selenium-tellurium compound bond layer that adhesively bonds the substrates to each other. Elemental compounds or amorphous compounds can be used for the materials of the first and second multi-stacked layers to form a polycrystalline or amorphous compound bond layer respectively. One advantage of the compound bond layer is that it can be dissolved using a selective wet etching material so that the active substrate and the base substrate can be non-destructively detached from each other.

公开(公告)号：US06777260B1

公开(公告)日：2004-08-17

申请号：US10641490

申请日：2003-08-14

申请人： Bomy Chen

发明人： Bomy Chen

IPC分类号： H01L2106

CPC分类号： H01L21/76802

摘要： A method of forming sub-lithographic sized contact holes in semiconductor material, which includes forming layers of etch mask materials, and forming intersecting first and second trenches in the etch mask layers, where through-holes are formed completely through the etch mask layers only where the first and second trenches intersect. The first and second trenches are made by the formation and subsequent removal of very thin vertical layers of material. The width dimensions of the trenches, and therefore of the through-holes, are sub-lithographic because they are dictated by the thickness of the thin vertical layers of material, and not by conventional photo lithographic processes used to form those vertical layers of material. The sub-lithographic through-holes are then used to etch sub-lithographic sized contact holes in underlying semiconductor materials.

摘要翻译： 一种在半导体材料中形成次光刻尺寸的接触孔的方法，其包括形成蚀刻掩模材料层，并在蚀刻掩模层中形成相交的第一和第二沟槽，其中通孔仅完全穿过蚀刻掩模层， 第一和第二沟槽相交。 第一和第二沟槽通过形成并随后去除非常薄的垂直材料层而制成。 沟槽的宽度尺寸，因此通孔的尺寸是亚光刻的，因为它们由薄的垂直材料层的厚度决定，而不是通过用于形成这些垂直材料层的常规光刻工艺。 然后使用亚光刻通孔来蚀刻下面的半导体材料中的次光刻尺寸的接触孔。

公开(公告)号：US06744076B2

公开(公告)日：2004-06-01

申请号：US10247539

申请日：2002-09-20

申请人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

发明人： Hiroyuki Fukuyama ,  Kazuhiro Nagata ,  Wataru Nakao

IPC分类号： H01L2106

CPC分类号： H01L33/32 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02658

摘要： A single crystalline aluminum nitride laminated substrate comprising a single crystalline &agr;-Al2O3 substrate such as a sapphire substrate, an aluminum oxynitride layer formed on the substrate and a single crystalline aluminum nitride film as the outermost layer, wherein the dislocation density in the single crystalline aluminum nitride is 108/cm2 or less. The above single crystalline aluminum nitride laminated substrate is formed by nitriding the substrate by heating in the presence of carbon, nitrogen and carbon monoxide. The above single crystalline aluminum nitride film has a law dislocation density, little lattice mismatching and excellent crystallinity. A Group III element nitride film having excellent luminous efficiency can be formed on this aluminum nitride film. The above laminated substrate is used in a base substrate for a Group III element nitride film, a light emitting device and a surface acoustic wave device.

摘要翻译： 包括单晶Al-Al 2 O 3衬底（例如蓝宝石衬底），形成在衬底上的氧氮化铝层和单晶氮化铝膜作为最外层的单晶氮化铝层压衬底，其中单晶铝中的位错密度 氮化物为10 8 / cm 2以下。上述单晶氮化铝层叠基板通过在碳，氮和一氧化碳的存在下加热氮化基板而形成。上述单晶氮化铝膜具有 法位错密度小，晶格不匹配，结晶性好。 可以在该氮化铝膜上形成具有优异发光效率的III族元素氮化物膜。 上述层叠基板用于III族元素氮化物膜的基底基板，发光元件和弹性表面波元件。

公开(公告)号：US06291832B1

公开(公告)日：2001-09-18

申请号：US09557679

申请日：2000-04-25

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L2106

CPC分类号： B82Y10/00 ,  H01L29/66151 ,  H01L29/882

摘要： A method/system for forming a resonant tunneling diode latch is disclosed. The method/system comprises the steps of forming a gate on a silicon substrate, the silicon substrate having at least one SOI layer disposed therein, providing an oxide spacer over the gate, providing a first ion implant in a first region of the silicon substrate, and then providing an oxide layer. The method further comprises polishing the oxide back to the gate, removing the gate, providing a second ion implant in a second region of the silicon substrate wherein the first and second regions have an undoped portion of silicon there between. According to the present invention, the method/system for forming a resonant tunneling diode latch in an SOI substrate that is easily implemented and results in an increased throughput of resonant tunneling diode devices.

摘要翻译： 公开了一种用于形成谐振隧穿二极管锁存器的方法/系统。 所述方法/系统包括以下步骤：在硅衬底上形成栅极，所述硅衬底具有设置在其中的至少一个SOI层，在所述栅极上提供氧化物间隔物，在所述硅衬底的第一区域中提供第一离子注入， 然后提供氧化物层。 该方法还包括将氧化物抛光回到栅极，去除栅极，在硅衬底的第二区域中提供第二离子注入，其中第一和第二区域之间具有未掺杂的硅部分。 根据本发明，在SOI衬底中形成谐振隧穿二极管锁存器的方法/系统容易实现，并且导致谐振隧道二极管器件的吞吐量增加。

公开(公告)号：US06800504B2

公开(公告)日：2004-10-05

申请号：US10285463

申请日：2002-11-01

申请人： Jiutao Li ,  Allen McTeer

发明人： Jiutao Li ,  Allen McTeer

IPC分类号： H01L2106

CPC分类号： C23C14/5846 ,  C23C14/0623 ,  C23C14/544 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/1658

摘要： Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

公开(公告)号：US06759675B2

公开(公告)日：2004-07-06

申请号：US09994182

申请日：2001-11-26

申请人： Sebastian Csutak ,  Wei E. Wu

发明人： Sebastian Csutak ,  Wei E. Wu

IPC分类号： H01L2106

CPC分类号： H01L27/1446 ,  G02B5/18 ,  H01L31/02327

摘要： An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.

摘要翻译： 光学器件在一个实施例中使用一个或多个掺杂的凹穴来增加光吸收区域的一个或多个边缘处的电场，以提高光学器件的效率。 在替代实施例中，光学器件使用覆盖的光阻层降低更高掺杂区域内的光吸收。 一些实施例使用用于光学装置的梳状结构来减小电容并产生平面CMOS兼容结构。

公开(公告)号：US06511862B2

公开(公告)日：2003-01-28

申请号：US09896009

申请日：2001-06-30

申请人： Stephen J. Hudgens ,  Tyler A. Lowrey

发明人： Stephen J. Hudgens ,  Tyler A. Lowrey

IPC分类号： H01L2106

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.