Pattern-forming method and method for manufacturing semiconductor device
    32.
    发明授权
    Pattern-forming method and method for manufacturing semiconductor device 有权
    用于制造半导体器件的图案形成方法和方法

    公开(公告)号:US08809207B2

    公开(公告)日:2014-08-19

    申请号:US14000643

    申请日:2012-02-20

    IPC分类号: H01L21/00

    摘要: A pattern-forming method for forming a predetermined pattern serving as a mask when etching film on a substrate includes the steps of: an organic film pattern-forming step for forming an organic film pattern on a film to be processed; forming a silicon nitride film on the organic film pattern; etching the silicon nitride film so that the silicon nitride film remains only on the lateral wall sections of the organic film pattern; and removing the organic film, thereby forming the predetermined silicon nitride film pattern on the film to be processed on a substrate. With the temperature of the substrate maintained at no more than 100° C., the film-forming step excites a processings gas and generates a plasma, performs plasma processing with the plasma, and forms a silicon nitride film having stress of no more than 100 MPa.

    摘要翻译: 当在基板上刻蚀膜时,用于形成用作掩模的预定图案的图案形成方法包括以下步骤:在待处理的膜上形成有机膜图案的有机膜图案形成步骤; 在有机膜图案上形成氮化硅膜; 蚀刻氮化硅膜,使得氮化硅膜仅保留在有机膜图案的侧壁部分上; 除去有机膜,从而在基板上形成预定的氮化硅膜图案。 在基板的温度保持不超过100℃的条件下,成膜步骤激发处理气体并产生等离子体,用等离子体进行等离子体处理,形成压力不超过100的氮化硅膜 MPa。

    Aftertreatment method for amorphous carbon film
    33.
    发明授权
    Aftertreatment method for amorphous carbon film 有权
    无定形碳膜后处理方法

    公开(公告)号:US08377818B2

    公开(公告)日:2013-02-19

    申请号:US12308828

    申请日:2007-07-04

    申请人: Hiraku Ishikawa

    发明人: Hiraku Ishikawa

    IPC分类号: H01L21/4763 H01L21/302

    摘要: The present invention is an aftertreatment method further applied to an amorphous carbon film to which a treatment including heating is performed after the film has been formed on a substrate. The treatment of preventing oxidation of the amorphous carbon film is performed immediately after the treatment including heating.

    摘要翻译: 本发明是进一步应用于在基板上形成膜之后进行包括加热处理的无定形碳膜的后处理方法。 在包括加热的处理之后立即进行防止非晶碳膜氧化的处理。

    Plasma processing method and semiconductor device
    37.
    发明授权
    Plasma processing method and semiconductor device 失效
    等离子体处理方法和半导体器件

    公开(公告)号:US06716725B1

    公开(公告)日:2004-04-06

    申请号:US09387771

    申请日:1999-09-01

    申请人: Hiraku Ishikawa

    发明人: Hiraku Ishikawa

    IPC分类号: H01L2120

    摘要: A wafer W is placed on a lower electrode 108 provided inside a processing chamber 102 of a CVD apparatus 100 and is heated to achieve a temperature equal to or greater than 350° C. and lower than 450° C. SiH4 and SiF4 with both their flow rates set at 20 sccm, B2H6 with its flow rate set at 7 sccm, O2 with its flow rate set at 200 sccm and Ar with its flow rate set at 400 sccm are introduced into the processing chamber 102, and a pressure within the range of 0.01 Torr˜10 Torr is set. 20 W/cm2 power at a frequency of 27.12 MHz and 10 W/cm2 power at a frequency of 400 kHz are respectively applied to an upper electrode 116 and the lower electrode 108 to generate plasma, and a layer insulating film 204 constituted of an SiOB film containing F is formed on the wafer W. With the B atoms incorporated into the molecular skeleton in the network structure of the SiOB film and the F atoms lowering the hygroscopicity by preventing formation of Si—OH bonds and the like, a dielectric constant of approximately 3.0 is achieved.

    摘要翻译: 将晶片W放置在设置在CVD装置100的处理室102内部的下电极108上,并加热以达到350℃以上且低于450℃的SiH 4和SiF 4, 流量设定在20sccm,B2H6,其流量设定为7sccm,O2,其流量设定在200sccm,Ar的流量设定为400sccm被引入到处理室102中,压力在该范围内 设定为0.01 Torr〜10 Torr。 分别在上电极116和下电极108上施加频率为27.12MHz,频率为400kHz的10W / cm 2功率的20W / cm 2功率,产生等离子体层 在晶片W上形成由包含F的SiOB膜构成的膜204.通过将Si原子并入SiOB膜的网状结构中的分子骨架中,并且F原子通过防止形成Si-OH键而降低吸湿性, 实现了大约3.0的介电常数。

    Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique
    39.
    发明授权
    Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique 失效
    在加压蒸汽环境中使用热处理装置的半导体装置作为平面化技术

    公开(公告)号:US06319847B1

    公开(公告)日:2001-11-20

    申请号:US09050561

    申请日:1998-03-30

    申请人: Hiraku Ishikawa

    发明人: Hiraku Ishikawa

    IPC分类号: H01L2131

    摘要: A method for manufacturing a semiconductor device comprises forming a silicon nitride film, a BPSG film, and a SOG silicon oxide film containing boron or phosphorous on a transistor element, thermally treating the resultant wafer in a pressurized steam ambient, and thermally treating the wafer in an inactive gas ambient. The first thermal treatment causes hydrolysis of the SOG film to form a gel state of the SOG film, whereas the second thermal treatment hardens the SOG film by removing H2O content in the SOG film. The phosphorous or boron in the SOG film weakens the bonds in —Si—O—Si— chains in the SOG film to assist the separation of the —Si—O—Si— chains and the planarization of the SOG film.

    摘要翻译: 一种制造半导体器件的方法包括在晶体管元件上形成氮化硅膜,BPSG膜和含有硼或磷的SOG氧化硅膜,在加压蒸汽环境中对所得晶片进行热处理,并将晶片热处理 惰性气体环境。 第一次热处理导致SOG膜的水解形成SOG膜的凝胶状态,而第二次热处理通过除去SOG膜中的H 2 O含量来硬化SOG膜。 SOG膜中的磷或硼减弱SOG膜中-Si-O-Si-链中的键,有助于分离-Si-O-Si-链和SOG膜的平坦化。

    Wiring layer in semiconductor device
    40.
    发明授权
    Wiring layer in semiconductor device 失效
    半导体器件中的接线层

    公开(公告)号:US5894170A

    公开(公告)日:1999-04-13

    申请号:US912067

    申请日:1997-08-15

    申请人: Hiraku Ishikawa

    发明人: Hiraku Ishikawa

    摘要: A semiconductor device includes (a) a semiconductor substrate, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a wiring layer having a thickness T and a width W1 greater than the thickness T formed on the first interlayer insulating film, the wiring layer being divided into a plurality of wiring layer segments each of which has a width W2 equal to or smaller than the thickness T, and (d) a second interlayer insulating film covering the wiring layer segments therewith. The semiconductor device ensures that even when a second interlayer insulating film is formed on a wiring layer by means of bias sputtering or bias CVD, projections are not formed on the second interlayer insulating film above the wiring layer. Namely, it is possible to completely planarize the second interlayer insulating film.

    摘要翻译: 半导体器件包括(a)半导体衬底,(b)形成在半导体衬底上的第一层间绝缘膜,(c)具有厚度T和宽度W1大于形成在第一层间绝缘体上的厚度T的布线层 所述布线层被分成多个布线层段,每个所述布线层段的宽度W2等于或小于所述厚度T;以及(d)覆盖所述布线层段的第二层间绝缘膜。 半导体器件确保即使当通过偏置溅射或偏压CVD在布线层上形成第二层间绝缘膜时,也不会在布线层上方的第二层间绝缘膜上形成突起。 即,可以使第二层间绝缘膜完全平坦化。