公开(公告)号：US20120012837A1

公开(公告)日：2012-01-19

申请号：US13175542

申请日：2011-07-01

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225

摘要： A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(εra/εrb)

摘要翻译： 具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。 第一晶体管和第二晶体管被设置为至少部分地彼此重叠。 第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（＆egr; rb /＆egr; ra）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示厚度 绝缘层的介电常数表示绝缘层的介电常数，rb表示绝缘层的介电常数。

公开(公告)号：US20110254538A1

公开(公告)日：2011-10-20

申请号：US13085606

申请日：2011-04-13

申请人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

发明人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

IPC分类号： G01R19/00

CPC分类号： G01R31/2601 ,  G01R19/0092

摘要： One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.

摘要翻译： 一个目的是提供一种用于测量可以测量微小电流的电流的方法。 流过电气元件的电流的值不是直接测量的，而是根据在预定周期内观察到的电位的变化计算出的。 用于测量电流的方法包括以下步骤：将预定电位施加到具有第一端子和第二端子的电气元件的第一端子; 测量连接到第二终端的节点的电位变化量; 以及根据所述电位变化量计算在所述电气元件的所述第一端子和所述第二端子之间流动的电流值。 因此，可以测量微小电流的值。

公开(公告)号：US20110246837A1

公开(公告)日：2011-10-06

申请号：US13133718

申请日：2010-10-13

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/34

CPC分类号： G06F11/079 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/3452 ,  G06Q10/02

摘要： In a system operations management apparatus, a burden to a system administrator when providing a decision criterion in detection of a failure in the future is reduced. The system operations management apparatus 1 includes a performance information accumulation unit 12, a model generation unit 30 and an analysis unit 31. The performance information accumulation unit 12 stores performance information including a plurality of types of performance values in a system in time series. The model generation unit 30 generates a correlation model including one or more correlations between the different types of performance values stored in the performance information accumulation unit 12 for each of a plurality of periods having one of a plurality of attributes. The analysis unit 31 performs abnormality detection of the performance information of the system which has been inputted by using the inputted performance information and the correlation model corresponding to the attribute of a period in which the inputted performance information has been acquired.

摘要翻译： 在系统运行管理装置中，降低了在检测未来的故障时提供判定准则时对系统管理员的负担。 系统运行管理装置1包括演奏信息存储单元12，模型生成单元30和分析单元31.演奏信息存储单元12以时间序列存储包括系统中的多种类型的演奏值的演奏信息。 模型生成单元30对于具有多个属性中的一个的多个周期中的每一个，生成包括存储在演奏信息存储单元12中的不同类型的演奏值之间的一个或多个相关性的相关模型。 分析单元31通过使用输入的演奏信息和与已经获取了输入的演奏信息的时段的属性相对应的相关模型来执行已经输入的系统的演奏信息的异常检测。

公开(公告)号：US20110227062A1

公开(公告)日：2011-09-22

申请号：US13044674

申请日：2011-03-10

申请人： Kiyoshi Kato ,  Satohiro Okamoto ,  Shuhei Nagatsuka

发明人： Kiyoshi Kato ,  Satohiro Okamoto ,  Shuhei Nagatsuka

IPC分类号： H01L27/108

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/13 ,  H01L28/60

摘要： A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a ions time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.

摘要翻译： 使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。 当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以保存离子时间的数据。 各半导体装置的存储单元中的包含氧化物半导体的晶体管串联连接， 因此，包括存储单元中的氧化物半导体的晶体管的源极和在相邻的存储单元中包括氧化物半导体的晶体管的漏电极可以彼此连接。 因此，可以减少存储单元占用的面积。

公开(公告)号：US07975186B2

公开(公告)日：2011-07-05

申请号：US12391435

申请日：2009-02-24

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G06F11/00

CPC分类号： G06F11/3447 ,  G06F11/3409 ,  G06F2201/81

摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first series of performance information that indicates time series variation about a first element and a second series of performance information that indicates time series variation about a second element, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a correlation change analysis unit which analyzes a change in the correlation model based on the performance information acquired newly which has not been used for generation of the correlation model.

摘要翻译： 一种操作管理装置，其从多个受控单位取得多个演奏项目的演奏信息，并管理被控制的单位的动作，包括：相关模型生成部，其将表示时刻的第一系列演奏信息， 关于第一元素的系列变化和指示关于第二元素的时间序列变化的第二系列性能信息，基于相关函数在第一元素和第二元素之间生成相关模型，并获得每个元素对的相关模型 以及相关变化分析单元，其基于未被用于生成相关模型的新获得的性能信息来分析相关模型的变化。

公开(公告)号：US20110148463A1

公开(公告)日：2011-06-23

申请号：US12966513

申请日：2010-12-13

申请人： Kiyoshi Kato ,  Jun Koyama

发明人： Kiyoshi Kato ,  Jun Koyama

IPC分类号： H03K19/173

CPC分类号： H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.

摘要翻译： 提供了一种新颖的非易失性锁存电路和使用非易失性锁存电路的半导体器件。 锁存电路具有环形结构，其中第一元件的输出电连接到第二元件的输入，并且第二元件的输出通过第二晶体管电连接到第一元件的输入端。 使用使用氧化物半导体作为沟道形成区域的半导体材料的晶体管作为开关元件，并且提供电容器以电连接到晶体管的源电极或漏电极，由此锁存电路的数据可以 并且可以形成非易失性锁存电路。

公开(公告)号：US20110148455A1

公开(公告)日：2011-06-23

申请号：US12967230

申请日：2010-12-14

申请人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri

IPC分类号： G01R31/26 ,  G01R19/00 ,  G01R27/26

CPC分类号： G01R31/275 ,  G01R19/0092 ,  G01R31/2884 ,  G09G3/20 ,  G09G2320/029

摘要： An object is to provide a current measurement method which enables a minute current to be measured. To achieve this, the value of a current flowing through an electrical element is not directly measured, but is calculated from a change in potential observed in a predetermined period. The detection of a minute current can be achieved by a measurement method including the steps of applying a predetermined potential to a first terminal of an electrical element comprising the first terminal and a second terminal; measuring an amount of change in potential of a node connected to the second terminal; and calculating, from the amount of change in potential, a value of a current flowing between the first terminal and the second terminal of the electrical element.

摘要翻译： 目的在于提供能够测量微小电流的电流测量方法。 为了实现这一点，不直接测量流过电气元件的电流的值，而是根据在预定周期内观察到的电位变化来计算。 可以通过测量方法来实现微小电流的检测，包括以下步骤：将预定电位施加到包括第一端子和第二端子的电气元件的第一端子; 测量连接到第二终端的节点的电位变化量; 以及根据电位变化量计算在电气元件的第一端子和第二端子之间流动的电流的值。

公开(公告)号：US20110147737A1

公开(公告)日：2011-06-23

申请号：US12966611

申请日：2010-12-13

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L29/12

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

摘要翻译： 第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 并且设置包括第二源电极和第二漏电极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏极之一重叠的电极。 第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

公开(公告)号：US20110128777A1

公开(公告)日：2011-06-02

申请号：US12952609

申请日：2010-11-23

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/24 ,  H01L29/12 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C16/0425 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

摘要翻译： 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管形成在包括半导体材料的衬底上或衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US20110121286A1

公开(公告)日：2011-05-26

申请号：US12949641

申请日：2010-11-18

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/092

CPC分类号： H01L21/02554 ,  G11C11/403 ,  G11C11/405 ,  G11C16/0425 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02664 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件。 半导体器件包括彼此串联连接的存储单元和电容器。 一个存储单元包括连接到位线和源极线的第一晶体管，连接到信号线和字线的第二晶体管，以及连接到字线的电容器。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极，第二晶体管的源电极和漏电极之一以及电容器的一个电极彼此连接。