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31.发明授权公开(公告)号：US06922113B2
公开(公告)日：2005-07-26
申请号：US10718608
申请日：2003-11-24
IPC分类号： G06F1/08 , G06F1/10 , H03K3/0231 , H03K3/03 , H03L7/00 , H03L7/081 , H03L7/089 , H03L7/099 , H03L7/18 , H03B27/00
CPC分类号： H03L7/0805 , G06F1/10 , H03K3/0231 , H03K3/03 , H03K3/0322 , H03L7/00 , H03L7/0812 , H03L7/0891 , H03L7/0995 , H03L7/18
摘要： The oscillation circuit includes at least two ring oscillation circuits in each of which a plurality of inverters are connected in a ring shape in a multi-stage fashion, and a conductive wiring line. The output of at least one inverter of each of the ring oscillation circuits is connected to the conductive wiring line, whereby the plurality of ring oscillators are caused to oscillate at an identical frequency. A PLL is constructed in such a way that the oscillation circuit obtained by the above means is formed into a voltage-controlled oscillation circuit, and that a phase-frequency comparator, a charge pump circuit and a low-pass filter are employed.
摘要翻译： 振荡电路包括至少两个环形振荡电路，其中多个反相器以多级方式连接成环状，并且具有导电布线。 每个环形振荡电路的至少一个反相器的输出端连接到导电布线，从而使多个环形振荡器以相同的频率振荡。 PLL被构造成使得通过上述装置获得的振荡电路形成为压控振荡电路，并且采用相位 - 频率比较器，电荷泵电路和低通滤波器。
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公开(公告)号：US06630857B2
公开(公告)日：2003-10-07
申请号：US10024039
申请日：2001-12-21
IPC分类号： H03K301
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit having at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.
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公开(公告)号：US06380798B1
公开(公告)日：2002-04-30
申请号：US09390962
申请日：1999-09-07
IPC分类号： H03K301
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit having at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.
摘要翻译： 半导体集成电路装置包括具有至少一个MOS晶体管的第一受控电路和用于产生MOS晶体管的衬底偏置电压的衬底偏置控制单元，其中当衬底偏置控制单元设置在第一模式时，相对较大 允许电流在MOS晶体管的源极和漏极之间流动，而当衬底偏置控制单元设置为第二模式时，允许在MOS晶体管的源极和漏极之间流动的较大电流被控制为电流 价值较小。 施加到第一受控电路的衬底偏置的值在PMOS晶体管的衬底偏压的第二模式中比在第一模式中大，而在第二模式中比在用于NMOS的衬底偏置的第一模式更小 晶体管。 施加到第一受控电路的电源电压在第二模式中被控制为比在第一模式中更小的值。
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公开(公告)号：US07598796B2
公开(公告)日：2009-10-06
申请号：US11987073
申请日：2007-11-27
IPC分类号： G05F1/10
CPC分类号： H01L27/0207 , G11C5/14 , G11C5/146 , G11C5/147 , H01L27/0928 , H01L27/11807 , H01L2924/0002 , H03K19/0016 , H01L2924/00
摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括用于控制的开关晶体管（MN1和MP1） 将要施加到衬底的电压和从衬底偏置控制电路输出的控制信号输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。
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公开(公告)号：US20060176101A1
公开(公告)日：2006-08-10
申请号：US11396543
申请日：2006-04-04
IPC分类号： G05F1/10
CPC分类号： H01L27/0207 , G11C5/14 , G11C5/146 , G11C5/147 , H01L27/0928 , H01L27/11807 , H01L2924/0002 , H03K19/0016 , H01L2924/00
摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc. which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，其保持高质量，本发明的半导体IC单元被构成为包括主电路（LOG ），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且所述主电路包括：开关晶体管（MN 1和MP 1），用于 控制施加到基板的电压和从基板偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到基板偏置控制电路。
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公开(公告)号：US06946865B2
公开(公告)日：2005-09-20
申请号：US10619601
申请日：2003-07-16
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit apparatus includes a first controlled circuit halving at least one MOS transistor and a substrate bias control unit for generating a substrate bias voltage of the MOS transistor, wherein when the substrate bias control unit is set in a first mode, a comparatively large current is allowed to flow between the source and drain of the MOS transistor, while when the substrate bias control unit is set in a second mode, the comparatively large current allowed to flow between the source and drain of the MOS transistor is controlled to a current of smaller value. The value of the substrate bias applied to the first controlled circuit is larger in the second mode than in the first mode for the substrate bias of the PMOS transistor, and smaller in the second mode than in the first mode for the substrate bias of the NMOS transistor. The power supply voltage applied to the first controlled circuit is controlled to a smaller value in the second mode than in the first mode.
摘要翻译： 一种半导体集成电路装置，包括：至少一个MOS晶体管的第一受控电路和用于产生MOS晶体管的衬底偏置电压的衬底偏置控制单元，其中当衬底偏置控制单元设置在第一模式时，相对较大 允许电流在MOS晶体管的源极和漏极之间流动，而当衬底偏置控制单元设置为第二模式时，允许在MOS晶体管的源极和漏极之间流动的较大电流被控制为电流 价值较小。 施加到第一受控电路的衬底偏置的值在PMOS晶体管的衬底偏压的第二模式中比在第一模式中大，而在第二模式中比在用于NMOS的衬底偏置的第一模式更小 晶体管。 施加到第一受控电路的电源电压在第二模式中被控制为比在第一模式中更小的值。
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37.发明授权Processor for controlling substrate biases in accordance to the operation modes of the processor 有权用于根据处理器的操作模式控制衬底偏压的处理器公开(公告)号：US06715090B1
公开(公告)日：2004-03-30
申请号：US09308488
申请日：1999-05-20
申请人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro Totsuka , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F130
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。
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公开(公告)号：US06683503B2
公开(公告)日：2004-01-27
申请号：US09141343
申请日：1998-08-27
IPC分类号： H03B2700
CPC分类号： H03L7/0805 , G06F1/10 , H03K3/0231 , H03K3/03 , H03K3/0322 , H03L7/00 , H03L7/0812 , H03L7/0891 , H03L7/0995 , H03L7/18
摘要： An oscillation circuit provides clock signals and a clock distribution circuit or system of circuits having low skew and low jitter to logic circuits and memory circuits of a microprocessor or the like. Further, a semiconductor integrated circuit device of high speed is provided as a result of the stable clock signal that is generated and distributed. The oscillation circuit is in a semiconductor integrated circuit device having a plurality of oscillators each having an oscillation node, wherein the oscillation nodes of each of the oscillators are connected together by a conductive wiring line that may be a closed loop. The oscillators are synchronized to oscillate at substantially the same frequency. The oscillators are connected to the conductive wiring line at connecting points having substantially the same interval of conductive wiring lengths between the connection points, which leads to synchronizing the oscillators to oscillate with a substantially identical phase. The conductive wiring line can also be formed in the shape of a mesh with the interval of length of the conductive wiring line between the connection points being at least 50 &mgr;m. The oscillators are ring oscillation circuits having inverters connected in a ring shape wherein an output of at least one inverter of each ring oscillation circuit is connected to the conductive wiring. Alternatively, the oscillators may be delay lines having multistage connected inverters with at least one inverter connected to the conductive wiring line.
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公开(公告)号：US20100005324A1
公开(公告)日：2010-01-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。
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公开(公告)号：US06525985B2
公开(公告)日：2003-02-25
申请号：US09577366
申请日：2000-05-23
IPC分类号： G11C514
CPC分类号： G11C7/18 , G06F12/0893 , G11C5/063 , G11C7/06 , G11C7/22 , G11C2207/108 , Y02D10/13
摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.
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