公开(公告)号：US10418377B2

公开(公告)日：2019-09-17

申请号：US15855692

申请日：2017-12-27

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11521 ,  H01L21/768 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11568 ,  H01L21/311 ,  H01L45/00 ,  H01L27/24 ,  H01L27/1159 ,  H01L27/11597

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.

公开(公告)号：US10403627B2

公开(公告)日：2019-09-03

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/528 ,  H01L27/108 ,  G11C11/405 ,  H01L21/8254 ,  G11C11/4097 ,  G11C13/00 ,  G11C5/04 ,  H01L25/065 ,  G11C11/4076 ,  H01L49/02 ,  G11C11/4094

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US20180233512A1

公开(公告)日：2018-08-16

申请号：US15855692

申请日：2017-12-27

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L27/11521 ,  H01L21/768 ,  H01L29/10 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124

Abstract: The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a method of fabricating a memory device comprises providing, on a substrate, an alternating stack of control gate layers and dielectric layers. The method additionally includes forming a memory block. comprising forming at least one memory hole through the alternating stack, where the at least one memory hole comprises on its sidewalls a stack of a programmable material, a channel material and a dielectric material, thereby forming at least one memory cell. The method additionally comprises removing a portion of the alternating stack to form at least one trench, where the at least one trench forms at least part of a boundary of the memory block. The method additionally comprises partially removing the control gate layers exposed at a sidewall of the at least one trench, thereby forming recesses in the control gate layers. The method further comprises filling the recesses with an electrically conductive material, thereby forming electrically conductive plugs. In another aspect, a device formed using the method is also provided.

公开(公告)号：US20160181259A1

公开(公告)日：2016-06-23

申请号：US14998227

申请日：2015-12-23

Applicant: IMEC VZW

Inventor： Jan Van Houdt ,  Pieter Blomme

IPC: H01L27/115 ,  G11C11/22 ,  H01L21/28

CPC classification number: H01L27/1159 ,  G11C11/2273 ,  H01L21/28291 ,  H01L27/11597 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及铁电存储器件及其制造和使用方法。 一方面，垂直铁电存储器件包括形成在半导体衬底上的一叠水平层，其中堆叠层包括与多个绝缘层交替的多个栅极电极层。 垂直结构垂直延伸穿过水平层堆叠，其中垂直结构具有垂直沟道结构，并且在其上形成有垂直过渡金属氧化物（TMO）铁电层的侧壁。 在栅极电极层和垂直沟道结构之间的每个重叠区域处形成存储单元。