公开(公告)号：US20240063133A1

公开(公告)日：2024-02-22

申请号：US17891536

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Beomseok Choi ,  Feras Eid ,  Omkar Karhade ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3128 ,  H01L21/56 ,  H01L21/4853 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08225 ,  H01L2224/08145

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.

公开(公告)号：US11895815B2

公开(公告)日：2024-02-06

申请号：US16909269

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel Elsherbini ,  Feras Eid

IPC: H01R12/53 ,  H05K9/00 ,  H01B7/18 ,  H01B7/00

CPC classification number: H05K9/0098 ,  H01B7/0018 ,  H01B7/1805 ,  H01R12/53

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

公开(公告)号：US11694986B2

公开(公告)日：2023-07-04

申请号：US17500824

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L21/76898 ,  H01L21/82 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/24147 ,  H01L2224/24155

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11688729B2

公开(公告)日：2023-06-27

申请号：US16030196

申请日：2018-07-09

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Krishna Bharath ,  Mathew Manusharow

IPC: H01L27/01 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L27/016 ,  H01L23/49816 ,  H01L23/49827 ,  H01L28/87 ,  H01L28/91

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230099827A1

公开(公告)日：2023-03-30

申请号：US17484281

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Wenhao Li ,  Stephen Morein ,  Yoshihiro Tomita

IPC: H01L23/532 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098020A1

公开(公告)日：2023-03-30

申请号：US17484384

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Henning Braunisch ,  Adel Elsherbini ,  Thomas L. Sounart ,  Johanna Swan

IPC: H01L23/473 ,  H01L23/50 ,  H05K7/20 ,  H01L23/31

Abstract: Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US11594801B2

公开(公告)日：2023-02-28

申请号：US16613070

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Sasha Oster ,  Telesphor Kamgaing ,  Erich Ewy ,  Kenneth Shoemaker ,  Adel Elsherbini ,  Johanna Swan

IPC: B60R11/04 ,  H01P3/16 ,  B60R16/023 ,  B60W40/02

Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

公开(公告)号：US20220415837A1

公开(公告)日：2022-12-29

申请号：US17359380

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff ,  Johanna Swan ,  Julien Sebot

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.