公开(公告)号：US20170031412A1

公开(公告)日：2017-02-02

申请号：US14812056

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的核心和耦合到核心的核心周边逻辑。 核心周界逻辑可以包括耦合到核的结构接口逻辑。 反过来，结构接口逻辑可以包括第一存储器，以在核心处于低功率状态时存储核心的状态信息，并且使得耦合在核心和核心之间的管芯间互连能够被维持在活动状态 在核心进入低功率状态期间。 描述和要求保护其他实施例。

公开(公告)号：US20160342515A1

公开(公告)日：2016-11-24

申请号：US15162707

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US20160231798A1

公开(公告)日：2016-08-11

申请号：US14614712

申请日：2015-02-05

Applicant: Intel Corporation

Inventor： Alexander Gendler

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a plurality of cores including a first core. The first core includes a first plurality of accumulator logics, each accumulator logic of the first plurality of accumulator logics to store corresponding first core telemetry data. The processor also includes a power management unit (PMU) to request telemetry data from the first core and in response to receive the first core telemetry data stored in at least one accumulator logic of the first plurality of accumulator logics. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括包括第一核心的多个核心。 第一核心包括第一多个累加器逻辑，第一多个累加器逻辑的每个累加器逻辑以存储对应的第一核心遥测数据。 处理器还包括电源管理单元（PMU），用于从第一核心请求遥测数据，并且响应于接收存储在第一多个累加器逻辑的至少一个累加器逻辑中的第一核心遥测数据。 描述和要求保护其他实施例。

公开(公告)号：US09378148B2

公开(公告)日：2016-06-28

申请号：US13843315

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0891 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US09256276B2

公开(公告)日：2016-02-09

申请号：US14039368

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.

公开(公告)号：US12124314B2

公开(公告)日：2024-10-22

申请号：US17207299

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Adwait Purandare ,  Ankush Varma ,  Nazar Haider ,  Daniela Kaufman ,  Gilad Bomstein ,  Shlomo Attias ,  Amit Gabai ,  Ariel Szapiro

IPC: G06F1/324 ,  G06F1/28 ,  G06F21/55 ,  G06F21/56 ,  G06F21/71 ,  G06F21/81

CPC classification number: G06F1/324 ,  G06F1/28 ,  G06F21/554 ,  G06F21/566 ,  G06F21/71 ,  G06F21/81 ,  G06F2221/034

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

公开(公告)号：US11809549B2

公开(公告)日：2023-11-07

申请号：US16728843

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

IPC: G06F21/00 ,  G06F21/54 ,  G06F1/32 ,  G06F21/56 ,  G06F9/38

CPC classification number: G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

公开(公告)号：US11762449B2

公开(公告)日：2023-09-19

申请号：US17563605

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3237

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/00

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US20230195199A1

公开(公告)日：2023-06-22

申请号：US17644677

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Madhusudan Chidambaram ,  Vishwesh Rudramuni ,  Shmuel Zobel ,  Alexander Gendler

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: In an embodiment, a processor may include a core domain comprising a plurality of processing cores, an uncore domain comprising an internal network, and a processor power management circuit. The processor power management circuit may be to: receive scalability hint values from the processing cores; determine a total core gain and a total uncore gain based at least in part on the scalability hint values; and distribute a frequency budget between the core domain and the uncore domain based at least in part on the total core gain and the total uncore gain. Other embodiments are described and claimed.

公开(公告)号：US20220326755A1

公开(公告)日：2022-10-13

申请号：US17739900

申请日：2022-05-09

Applicant: Intel Corporation

Inventor： Alexander Gendler

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.