公开(公告)号：US20190304840A1

公开(公告)日：2019-10-03

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan LEE ,  Everett S. CASSIDY-COMFORT ,  Joodong PARK ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Rahul RAMASWAMY ,  Neville L. DIAS ,  Hsu-Yu CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

公开(公告)号：US20190296114A1

公开(公告)日：2019-09-26

申请号：US16435301

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Gopinath BHIMARASETTI ,  Walid M. HAFEZ ,  Joodong PARK ,  Weimin HAN ,  Raymond E. COTNER ,  Chia-Hong JAN

IPC: H01L29/36 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US20190296105A1

公开(公告)日：2019-09-26

申请号：US16435250

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L29/808 ,  H01L29/66 ,  H01L29/8605 ,  H01L29/40 ,  H01L27/098

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US20190287972A1

公开(公告)日：2019-09-19

申请号：US16318316

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Roman W. OLAC-VAW ,  Chia-Hong JAN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L23/48 ,  H01L21/768 ,  H01L21/8238

Abstract: Dual fin endcaps for self-aligned gate edge architectures, and methods of fabricating dual fin endcaps for self-aligned gate edge architectures, are described. In an example, a semiconductor structure includes an I/O device having a first plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation layer. A logic device having a second plurality of semiconductor fins is disposed above the substrate and protrudes through the uppermost surface of the trench isolation layer. A gate edge isolation structure is disposed between the I/O device and the logic device. A semiconductor fin of the first plurality of semiconductor fins closest to the gate edge isolation structure is spaced farther from the gate edge isolation structure than a semiconductor fin of the second plurality of semiconductor fins closest to the gate edge isolation structure.

公开(公告)号：US20190206980A1

公开(公告)日：2019-07-04

申请号：US16328704

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L49/02 ,  H01L21/306 ,  H01L21/285 ,  C23C16/455

CPC classification number: H01L28/24 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/30608 ,  H01L27/0629

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

公开(公告)号：US20190157153A1

公开(公告)日：2019-05-23

申请号：US16253760

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L21/84 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L27/12 ,  H01L23/528

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20180145083A1

公开(公告)日：2018-05-24

申请号：US15575792

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Xiaoghong TONG ,  Walid M. HAFEZ ,  Zhiyong MA ,  Peng BAI ,  Chia-Hong JAN ,  Zhanping CHEN

IPC: H01L27/112 ,  G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252

Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.

公开(公告)号：US20230207569A1

公开(公告)日：2023-06-29

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/66545 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L29/6681 ,  H01L29/51 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823437 ,  H01L29/513 ,  H01L29/42356 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/6656

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20220130962A1

公开(公告)日：2022-04-28

申请号：US17569376

申请日：2022-01-05

Applicant: Intel Corporation

Inventor： Gopinath BHIMARASETTI ,  Walid M. HAFEZ ,  Joodong PARK ,  Weimin HAN ,  Raymond E. COTNER ,  Chia-Hong JAN

IPC: H01L29/36 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

公开(公告)号：US20220130871A1

公开(公告)日：2022-04-28

申请号：US17568652

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.