公开(公告)号：US20210028084A1

公开(公告)日：2021-01-28

申请号：US16518643

申请日：2019-07-22

Applicant: Intel Corporation

Inventor： Sergio Antonio Chan Arguedas ,  Edvin Cetegen ,  Baris Bicen ,  Aravindha R. Antoniswamy

IPC: H01L23/367 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package that includes a die, a thermal interface material (TIM) coupled with the die, and an integrated heat spreader (IHS) coupled with the TIM. The IHS may include a feature with a non-uniform cross-sectional profile that includes a thin point and a thick point as measured in a direction perpendicular to a face of the die to which the TIM is coupled. Other embodiments may be described or claimed.

公开(公告)号：US12002727B2

公开(公告)日：2024-06-04

申请号：US16788186

申请日：2020-02-11

Applicant: INTEL CORPORATION

Inventor： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/3185 ,  H01L23/3675 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/35121

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US20240136292A1

公开(公告)日：2024-04-25

申请号：US18400761

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Edvin Cetegen ,  Anurag Tripathi ,  Nitin A. Deshpande

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11901333B2

公开(公告)日：2024-02-13

申请号：US16596367

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11776821B2

公开(公告)日：2023-10-03

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L21/563 ,  H01L21/67126 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/564 ,  H05K2201/09045

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US11735495B2

公开(公告)日：2023-08-22

申请号：US16287653

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal

IPC: H01L23/46 ,  F28D15/02 ,  H01L21/48 ,  H01L23/427

CPC classification number: H01L23/46 ,  F28D15/02 ,  H01L21/4882 ,  H01L23/427

Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

公开(公告)号：US20230086180A1

公开(公告)日：2023-03-23

申请号：US17479854

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Onur Ozkan ,  Edvin Cetegen ,  Steve Cho ,  Nicholas S. Haehn ,  Jacob Vehonsky ,  Gang Duan

IPC: H01L23/00

Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

公开(公告)号：US11282717B2

公开(公告)日：2022-03-22

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

公开(公告)号：US20210391273A1

公开(公告)日：2021-12-16

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.