公开(公告)号：US20180218940A1

公开(公告)日：2018-08-02

申请号：US15926870

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US20160247715A1

公开(公告)日：2016-08-25

申请号：US15141522

申请日：2016-04-28

Applicant: INTEL CORPORATION

Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US20240282624A1

公开(公告)日：2024-08-22

申请号：US18649389

申请日：2024-04-29

Applicant: Intel Corporation

Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US20240112952A1

公开(公告)日：2024-04-04

申请号：US18535623

申请日：2023-12-11

Applicant: Intel Corporation

Inventor： Hui Jae YOO ,  Tejaswi K. INDUKURI ,  Ramanan V. CHEBIAM ,  James S. CLARKE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76849 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L21/76843 ,  H01L2224/45015 ,  H01L2924/0002

Abstract: A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC: H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20200105588A1

公开(公告)日：2020-04-02

申请号：US16702233

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L23/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

公开(公告)号：US20190385897A1

公开(公告)日：2019-12-19

申请号：US16463816

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Stephanie A. BOJARSKI ,  Kevin LIN ,  Marie KRYSAK ,  Tristan A. TRONIC ,  Hui Jae YOO ,  Jeffery D. BIELEFELD ,  Jessica M. TORRES

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.

公开(公告)号：US20190189500A1

公开(公告)日：2019-06-20

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20170372947A1

公开(公告)日：2017-12-28

申请号：US15686047

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.