公开(公告)号：US11870759B2

公开(公告)日：2024-01-09

申请号：US17744296

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Gregory Bowers

IPC: H04L29/06 ,  H04L9/40 ,  H04L9/08 ,  H04L69/324 ,  H04L69/16 ,  H04L69/321 ,  H04L69/164

CPC classification number: H04L63/0428 ,  H04L9/088 ,  H04L63/06 ,  H04L69/161 ,  H04L69/164 ,  H04L69/321 ,  H04L69/324

Abstract: Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

公开(公告)号：US11805081B2

公开(公告)日：2023-10-31

申请号：US16807014

申请日：2020-03-02

Applicant: Intel Corporation

Inventor： Linden Cornett ,  Noam Elati ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Eliel Louzoun ,  Manasi Deval

IPC: H04L49/901 ,  H04L69/16 ,  G06F12/0802 ,  H04L49/9057

CPC classification number: H04L49/901 ,  G06F12/0802 ,  H04L69/16 ,  G06F2212/154 ,  H04L49/9057

Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.

公开(公告)号：US11757973B2

公开(公告)日：2023-09-12

申请号：US17889678

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

IPC: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L9/40

CPC classification number: H04L67/02 ,  H04L63/0485 ,  H04L69/04 ,  H04L69/164 ,  H04L69/166 ,  H04L63/0428

Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

公开(公告)号：US11556437B2

公开(公告)日：2023-01-17

申请号：US16211950

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F9/455 ,  G06F9/46 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/48

Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

公开(公告)号：US20220394080A1

公开(公告)日：2022-12-08

申请号：US17889678

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

IPC: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L9/40

Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

公开(公告)号：US11474916B2

公开(公告)日：2022-10-18

申请号：US16211955

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/455 ,  G06F9/48

Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.

公开(公告)号：US20220278965A1

公开(公告)日：2022-09-01

申请号：US17744296

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Gregory Bowers

IPC: H04L9/40 ,  H04L9/08 ,  H04L69/324 ,  H04L69/16 ,  H04L69/321 ,  H04L69/164

Abstract: Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

公开(公告)号：US10768841B2

公开(公告)日：2020-09-08

申请号：US15721817

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Linden Cornett ,  Chih-Jen Chang ,  Manasi Deval ,  Parthasarathy Sarangam ,  Naru D. Sundar ,  Padma Akkiraju ,  Alexander Nguyen

IPC: G06F15/173 ,  G06F3/06 ,  G06F16/174 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  H04L12/24 ,  H04L29/08 ,  G06F11/30 ,  G06F9/50 ,  H03M7/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  G06F9/38 ,  G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/453 ,  H01R13/631 ,  H05K7/14 ,  H04L12/911 ,  G06F11/14 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.

公开(公告)号：US20190140967A1

公开(公告)日：2019-05-09

申请号：US16236429

申请日：2018-12-29

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Gregory J. Bowers

IPC: H04L12/805 ,  H04L29/06 ,  H04L12/741

Abstract: Technologies for protocol-agnostic network packet segmentation includes determining whether a size of a payload of a network packet to be transmitted by the compute device exceeds a maximum size threshold and segmenting the payload into a plurality of segmented payloads if the size of the payload exceeds the maximum size of threshold. The payload may be segmented based on segmentation metadata associated with the network packet.

公开(公告)号：US20160321203A1

公开(公告)日：2016-11-03

申请号：US15008083

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Yadong Li ,  Linden Cornett ,  Manasi Deval ,  Anil Vasudevan ,  Parthasarathy Sarangam

IPC: G06F13/24 ,  H04L29/06

CPC classification number: G06F13/24 ,  H04L69/165

Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.