公开(公告)号：US20190164815A1

公开(公告)日：2019-05-30

申请号：US16092722

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/528

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US20180122690A1

公开(公告)日：2018-05-03

申请号：US15573457

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0335 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76897 ,  H01L2224/16225

Abstract: Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.

公开(公告)号：US20170058401A1

公开(公告)日：2017-03-02

申请号：US15119699

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Grant M. KLOSTER ,  Florian GSTREIN ,  Harsono S. SIMKA ,  Paul A. ZIMMERMAN ,  Robert L. BRISTOL

IPC: C23C16/455 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  C23C16/18 ,  C23C16/48

CPC classification number: C23C16/45553 ,  C23C16/18 ,  C23C16/482 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/66795

Abstract: Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Abstract translation: 描述了光辅助金属原子层沉积（ALD）和化学气相沉积（CVD）的前体和工艺设计。 在一个实例中，制造薄金属膜的方法包括将前体分子引入靠近基底上或表面的表面，每个前体分子具有被配体包围的一个或多个金属中心。 该方法还涉及通过使用光辅助方法从前体分子解离配体而在表面上沉积金属层。