公开(公告)号：US20200226067A1

公开(公告)日：2020-07-16

申请号：US16828700

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Frank T. HADY ,  Sanjeev N. TRIKA

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F8/41

Abstract: An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.

公开(公告)号：US20190324683A1

公开(公告)日：2019-10-24

申请号：US16457982

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Peng LI ,  Jawad B. KHAN ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/1081

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US20190114114A1

公开(公告)日：2019-04-18

申请号：US16211108

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Steven C. MILLER

IPC: G06F3/06 ,  H03M13/15 ,  G06F11/10

Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.

公开(公告)号：US20190114096A1

公开(公告)日：2019-04-18

申请号：US16213642

申请日：2018-12-07

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a storage system management unit to manage a storage system having physical storage resources divided into different reliability zones. A data item to be stored in the storage system is to be assigned a particular reliability level by the management unit and is to be stored by the management unit in one of the reliability zones that is to provide a level of protection against data loss that is at least as protective as the particular reliability level.

公开(公告)号：US20190004715A1

公开(公告)日：2019-01-03

申请号：US15640169

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/121

Abstract: In one embodiment, a storage drive is configured to receive a selective flush command which causes the storage drive to selectively flush write data which has been identified in connection with the selective flush command, from volatile buffer memory to a nonvolatile storage memory. Conversely, write data stored in the volatile buffer memory which is not identified in connection with the selective flush command, may remain unaffected by the selective flush command, and thus may remain stored in the volatile buffer memory without being flushed to the nonvolatile storage memory as a result of the selective flush command. Other aspects are described herein.

公开(公告)号：US20180267706A1

公开(公告)日：2018-09-20

申请号：US15460043

申请日：2017-03-15

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/02 ,  G06F17/30

Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.

公开(公告)号：US20180189000A1

公开(公告)日：2018-07-05

申请号：US15394453

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0608 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7201

Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.

公开(公告)号：US20180173418A1

公开(公告)日：2018-06-21

申请号：US15385791

申请日：2016-12-20

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  Anand S. RAMALINGAM ,  Jawad B. KHAN ,  William K. LUI ,  Divya NARAYANAN ,  Sanjeev N. TRIKA

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

公开(公告)号：US20180095720A1

公开(公告)日：2018-04-05

申请号：US15282544

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vinodh GOPAL ,  Jawad B. KHAN ,  Sanjeev N. TRIKA

IPC: G06F7/20 ,  G06F17/30

CPC classification number: G06F7/20 ,  G06F16/2255 ,  G06F16/24553

Abstract: A storage device is described. The storage device includes non volatile memory having data storage resources organized into slots to store chunks of data. The storage device includes memory to store a data pointer table having groups of pointers to the slots. Each of the groups correspond to a respective block that is stored in the non volatile memory. Certain ones of the pointers are to have an associated set of hashes of different segments of the respective chunks that are pointed to by the certain ones of the pointers. The storage device includes a search module to implement a search function within the storage device that hashes a search key and compares the hashed search key to the hashes of the different segments to identify a possible match to the search key.

公开(公告)号：US20180090201A1

公开(公告)日：2018-03-29

申请号：US15276588

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Yi ZOU

IPC: G11C11/56 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C11/5628 ,  G06F11/1044 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: Provided are a method and apparatus for programming non-volatile memory using a multi-cell storage cell group to provide error location information for retention errors. Each storage cell in the non-volatile memory is programmed with threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller organizes the storage cells into storage cell groups, each storing m bits of information programmed with the threshold voltage levels. A determination is made of one threshold voltage level to use for each of the storage cells in the storage cell group to program a selected k bits in the storage cell group with threshold voltage levels defining one of a plurality of valid states. The threshold voltage levels for at least one of the storage cells of the storage cell group in any two valid states differ by at least two threshold voltage levels.