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公开(公告)号：US10552253B2
公开(公告)日：2020-02-04
申请号：US15741967
申请日：2015-09-26
Applicant: INTEL CORPORATION
Inventor： Venkatraman Iyer , Robert G. Blankenship , Mahesh Wagh , Zuoguo Wu
Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
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公开(公告)号：US20190288421A1
公开(公告)日：2019-09-19
申请号：US16431498
申请日：2019-06-04
Applicant: Intel Corporation
Inventor： Jong-Ru Guo , Yunhui Chu , Jun Liao , Kai Xiao , Jingbo Li , Yuanhong Zhao , Mo Liu , Beomtaek Lee , James A. McCall , Jaejin Lee , Xiaoning Ye , Zuoguo Wu , Xiang Li
Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.
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公开(公告)号：US20180276164A1
公开(公告)日：2018-09-27
申请号：US15761401
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L25/065 , H01L23/538
CPC classification number: G06F13/4027 , G06F13/4022 , G06F13/405 , G06F13/4265 , H01L23/5386 , H01L25/0655 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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公开(公告)号：US10050623B2
公开(公告)日：2018-08-14
申请号：US14865682
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Kai Xiao , Zuoguo Wu , Venkatraman Iyer
IPC: H03L5/00 , H03K19/0175 , H03K5/08 , G06F13/00 , H04L25/02
Abstract: A redriver device is provided to receive signals from a first device and forward the signals to a second device on a differential link. Detection circuitry is provided to detect presence of the second device on the link by detecting a pulldown voltage generated from termination of the second device on the link, and pulldown relay circuitry is provided to generate an emulated version of the pulldown voltage of the second device on pins to connect to the first device in response to detecting presence of the second device on the link.
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公开(公告)号：US20180196710A1
公开(公告)日：2018-07-12
申请号：US15741967
申请日：2015-09-26
Applicant: INTEL CORPORATION
Inventor： Venkatraman Iyer , Robert G. Blankenship , Mahesh Wagh , Zuoguo Wu
CPC classification number: G06F11/1004 , G06F13/16 , G06F2213/16 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0075 , H04L1/1607 , H04L1/20 , H04L29/06 , H04L2001/0094 , Y02D10/14
Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
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Patent Agency Ranking
36.发明授权Optical IO interconnect having a WDM architecture and CDR clock sharing receiver 有权具有WDM架构和CDR时钟共享接收器的光IO互连公开(公告)号：US09337939B2
公开(公告)日：2016-05-10
申请号：US13629945
申请日：2012-09-28
Applicant: Intel Corporation
Abstract: Systems and methods may provide for an optical module including an optical demultiplexer to receive a wavelength division multiplexed (WDM) signal from a single receive optical fiber and separate the WDM signal into a plurality of optical signals. Additionally, the optical module may include a receiver conversion unit to convert the plurality of optical signals into a corresponding plurality of electrical signals. In addition, the optical module may include a buffer chip having a single clock and data recovery (CDR) module to recover a clock from a designated signal in the plurality of electrical signals and distribute the recovered clock to a plurality of data lanes corresponding to the plurality of electrical signals.
Abstract translation: 系统和方法可以提供包括光解复用器的光模块，以从单个接收光纤接收波分复用（WDM）信号，并将WDM信号分离成多个光信号。 另外，光学模块可以包括将多个光信号转换为对应的多个电信号的接收机转换单元。 另外，光学模块可以包括具有单个时钟和数据恢复（CDR）模块的缓冲器芯片，以从多个电信号中的指定信号中恢复时钟，并将恢复的时钟分配给多个对应于 多个电信号。
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37.发明授权公开(公告)号：US12283994B2
公开(公告)日：2025-04-22
申请号：US17304556
申请日：2021-06-23
Applicant: Intel Corporation
Abstract: In one embodiment, an apparatus includes a processor, a laser, and a modulator. The processor is to generate a first electrical signal including first data and a second electrical signal including second data. The laser is to generate a multiplexed carrier signal comprising a first carrier signal and a second carrier signal, the laser to operate at a first laser power setting. The modulator is to generate a multiplexed optical signal including a first optical signal based in part on the first electrical signal and the first carrier signal and a second optical signal based in part on the second electrical signal and the second carrier signal. The apparatus is to transmit the multiplexed optical signal to a device and to retransmit the first data from the apparatus to the device based on a detection of error in a received version of the first data at the device. Other embodiments are described and claimed.
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公开(公告)号：US20240020259A1
公开(公告)日：2024-01-18
申请号：US18352785
申请日：2023-07-14
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Zuoguo Wu , Mahesh Wagh , Mohiuddin M. Mazumder , Venkatraman Iyer , Jeff C. Morriss
IPC: G06F13/40 , H01L25/065 , G06F13/42 , H01L23/538
CPC classification number: G06F13/4027 , H01L25/0655 , G06F13/4265 , G06F13/4022 , G06F13/405 , H01L23/5386 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.
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39.发明公开公开(公告)号：US20230369289A1
公开(公告)日：2023-11-16
申请号：US17742799
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Jong-Ru Guo , Zhen Zhou , Jason Mix , Chia-Pin Chiu , Zuoguo Wu
IPC: H01L25/065 , H01L23/31 , H01L23/498 , H01L25/00
CPC classification number: H01L25/0657 , H01L23/3157 , H01L23/49811 , H01L23/49838 , H01L25/50 , H01L2225/06506 , H01L2225/06548
Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.
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公开(公告)号：US11797378B2
公开(公告)日：2023-10-24
申请号：US17721290
申请日：2022-04-14
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Robert G. Blankenship , Mahesh Wagh , Zuoguo Wu
CPC classification number: G06F11/1004 , G06F13/16 , H04L1/00 , H04L1/0041 , H04L1/0045 , H04L1/0061 , H04L1/0075 , H04L1/20 , H04L9/40 , G06F2213/16 , H04L1/1607 , H04L2001/0094 , Y02D10/00
Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.
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