公开(公告)号：US11004856B1

公开(公告)日：2021-05-11

申请号：US16680965

申请日：2019-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Tenko Yamashita ,  Kangguo Cheng ,  Heng Wu

IPC: H01L27/11 ,  H01L27/06 ,  H01L27/092 ,  H01L23/528 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/822

Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

公开(公告)号：US20210111068A1

公开(公告)日：2021-04-15

申请号：US17131998

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments of the invention are directed to an integrated circuit. A non-limiting example of the integrated circuit includes a transistor formed over a substrate. A dielectric region is formed over the transistor and the substrate. A trench is positioned in the dielectric region and over a S/D region of the transistor. A first liner and a conductive plug are within the trench such that the first liner and the conductive plug are only present within a bottom portion of the trench. A substantially oxygen-free replacement liner and a S/D contact are within the top portion of the trench such that a bottom contact surface of the S/D contact directly couples to a top surface of the conductive plug.

公开(公告)号：US10916657B2

公开(公告)日：2021-02-09

申请号：US16410000

申请日：2019-05-13

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/311 ,  H01L29/08 ,  H01L21/3105 ,  H01L29/10 ,  H01L29/06

Abstract: A method of forming a semiconductor structure includes forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer. The method also includes forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer, performing a channel release to remove the second semiconductor layer, and performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer. The channel layer comprises an n-type field-effect transistor (NFET) channel.

公开(公告)号：US10910470B1

公开(公告)日：2021-02-02

申请号：US16515526

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Alexander Reznicek ,  Lan Yu

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

公开(公告)号：US10833079B2

公开(公告)日：2020-11-10

申请号：US16237935

申请日：2019-01-02

Applicant: International Business Machines Corporation

Inventor： Tenko Yamashita ,  Chen Zhang ,  Kangguo Cheng ,  Heng Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/3065 ,  H01L21/225 ,  H01L21/311 ,  H01L21/308 ,  H01L29/10 ,  H01L21/324 ,  H01L21/02 ,  H01L29/36 ,  H01L21/265

Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.

公开(公告)号：US20200328120A1

公开(公告)日：2020-10-15

申请号：US16379950

申请日：2019-04-10

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Kangguo Cheng ,  Chen Zhang ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

Abstract: A method of forming a semiconductor structure includes forming vertical fins comprising a first semiconductor layer, an isolation layer and a second semiconductor layer, the first and second semiconductor layers providing vertical transport channels for lower and upper vertical transport field-effect transistors (VTFETs) of a stacked VTFET structure. The method also includes forming a first gate stack for the lower VTFET surrounding a first portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack for the upper VTFET surrounding a second portion of the second semiconductor layer of the vertical fins. The first and second portions have different sizes such that the upper and lower VTFETs of the stacked VTFET structure have different effective gate widths.

公开(公告)号：US20200273755A1

公开(公告)日：2020-08-27

申请号：US16283995

申请日：2019-02-25

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Tenko Yamashita ,  Chen Zhang ,  Joshua M. Rubin

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/768 ,  H01L27/088

Abstract: A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure including one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower VTFET, an isolation layer, and a second semiconductor layer providing a vertical transport channel for an upper VTFET. The method also includes forming at least one vertical via in the stacked VTFET structure spaced apart from the one or more vertical fins. The method further includes forming at least one horizontal via extending from the vertical via to at least one source/drain region of at least one of the upper and lower VTFETs. The method further includes forming a contact liner in the horizontal via, forming a barrier layer on sidewalls of the vertical via and the contact liner, and forming a contact material over the barrier layer in the vertical via.

公开(公告)号：US10727323B2

公开(公告)日：2020-07-28

申请号：US15864685

申请日：2018-01-08

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Heng Wu

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/786 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78

Abstract: A method for manufacturing a transistor device includes forming a plurality of fins on a substrate, performing an annealing process to cause the fins to have a round shape, growing an epitaxial semiconductor layer on a surface of each fin, wherein the epitaxial semiconductor layer is formed along the round shape, and forming a gate structure on the substrate, wherein the gate structure is formed on the epitaxial semiconductor layer on the surface of each fin.

公开(公告)号：US20200235008A1

公开(公告)日：2020-07-23

申请号：US16252763

申请日：2019-01-21

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao

IPC: H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L21/8238

Abstract: Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench.

公开(公告)号：US20200152760A1

公开(公告)日：2020-05-14

申请号：US16738345

申请日：2020-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee ,  Heng Wu

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L29/08

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.