公开(公告)号：US20140281605A1

公开(公告)日：2014-09-18

申请号：US13837655

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

Abstract translation: 实施例包括一种用于管理计算机系统中的电力的方法，所述计算机系统包括主处理器和包括供电单元的主动存储器设备，所述主存储器设备通过存储器链路与主处理器通信，所述动力单元包括处理元件。 该方法包括主处理器在程序线程上执行程序，遇到要由有源存储器件执行的代码的第一部分，通过第一命令改变有源存储器件上的供电单元的功率状态，基于 主处理器遇到第一部分代码，第一个命令包括一个存储命令。 该方法还包括处理元件在第二时间执行代码的第一部分，基于执行第一部分的处理元件，将主处理器的功率状态从功率使用状态改变到省电状态。

公开(公告)号：US20140173224A1

公开(公告)日：2014-06-19

申请号：US13714724

申请日：2012-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/3877 ,  G06F11/00 ,  G06F13/00 ,  G06F15/785

Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.

Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器设备中的顺序位置访问。 一个方面包括用于顺序位置访问的方法，其包括从存储器接收与处理元件上的队列条目相关联的第一组数据值。 读取与队列条目相关联并且指定提取数据值的第一子集的位置的标签值。 队列条目用从标签值指定的位置开始的数据值的第一个子集填充。 处理元件确定第一组数据值中的数据值的第二子集是否与后续的队列条目相关联，并且用数据值的第二子集填充后续队列条目的一部分。

公开(公告)号：US20140129799A1

公开(公告)日：2014-05-08

申请号：US13671679

申请日：2012-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/10

CPC classification number: G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  Y02D10/13

Abstract: Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.

Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器件中的地址生成。 一方面包括在活动存储设备中产生地址的方法。 该方法包括从处理元件的寄存器文件组读取基地址值和偏移地址值。 处理元件根据基地址值和偏移地址值确定虚拟地址。 处理元件将虚拟地址转换为物理地址，并基于物理地址访问存储器中的位置。

公开(公告)号：US10049061B2

公开(公告)日：2018-08-14

申请号：US13674520

申请日：2012-11-12

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  James A. Kahle ,  Jaime H. Moreno ,  Ravi Nair

IPC: G06F12/10 ,  G06F13/28

Abstract: Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.

公开(公告)号：US09405711B2

公开(公告)日：2016-08-02

申请号：US13737339

申请日：2013-01-09

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/00 ,  G06F13/18 ,  G06F9/48 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract translation: 根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。 存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控​​制器。 存储器访问请求在存储器控制器处被接收。 将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。 存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

公开(公告)号：US09400656B2

公开(公告)日：2016-07-26

申请号：US13966408

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Bruce M. Fleischer ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3828

Abstract: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline.

Abstract translation: 实施例包括用于在暴露流水线处理元件中链接数据的方法。 该方法包括将多个指令字分离成第一子指令和第二子指令，在暴露流水线处理元件中接收第一子指令和第二子指令。 该方法还包括在第一时间发出第一子指令，在与第一时间不同的第二时间发出第二子指令，第二时间被补偿以考虑第二子指令对第一子指令的依赖性 来自第一子指令的结果是，第一流水线以第一时钟周期执行第一子指令，并将第一结果从执行第一子指令传送到耦合到第一流水线的链接总线和第二流水线， 在第一时钟周期之后的第二时钟周期中，其对应于第一管线中的锁存流水线级的总数。

公开(公告)号：US09390038B2

公开(公告)日：2016-07-12

申请号：US13966441

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Martin Ohmacht ,  Krishnan Sugavanam

IPC: G06F13/28 ,  H01L25/18 ,  G06F21/72 ,  G06F13/364 ,  G06F9/38

CPC classification number: G06F13/364 ,  G06F9/3826 ,  G06F13/28 ,  G06F21/72 ,  H01L25/18 ,  H01L2924/0002 ,  H04L2209/125 ,  Y02D10/14 ,  H01L2924/00

Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Abstract translation: 实施例包括用于旁路有源存储器件中的数据的方法。 该方法包括：请求者确定尚未传送给设保者的授权人的传送次数，根据满足阈值的传送次数，向互连网请求旁路路径用于传送，并通过 基于请求的设保人的旁路路径，互连网络根据请求授予设保人的控制权。 该方法还包括互连网络，其基于事件请求对设保人的控制，并且经由互连网络从其他请求者传送延迟的传输，延迟的传送由于授权者先前由请求者控制而延迟，基于控制进行通信 的设保人被改回互连网络。

公开(公告)号：US09274971B2

公开(公告)日：2016-03-01

申请号：US13685816

申请日：2012-11-27

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans m. Jacobson ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  Y02D10/13

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

公开(公告)号：US09268704B2

公开(公告)日：2016-02-23

申请号：US13787057

申请日：2013-03-06

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  Y02D10/13

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

Abstract translation: 根据一个实施例，提供了一种用于在包括与主动存储器设备通信的主处理器的系统中交换数据的方法。 该方法包括主动存储器装置中的处理元件，从主处理器接收指令，并从主处理器上运行的线程接收存储请求，存储请求指定与处理元件相关联的存储器地址。 该方法还包括将存储请求中提供的值存储在处理元件中的队列中，并且处理元件使用来自队列的值来执行指令。

公开(公告)号：US09110778B2

公开(公告)日：2015-08-18

申请号：US13671679

申请日：2012-11-08

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/02 ,  G06F12/06 ,  G06F12/10 ,  Y02D10/13

Abstract: Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the processing element. The processing element determines a virtual address based on the base address value and the offset address value. The processing element translates the virtual address into a physical address and accesses a location in the memory based on the physical address.

Abstract translation: 实施例涉及包括存储器和处理元件的有源存储器件中的地址生成。 一方面包括在活动存储设备中产生地址的方法。 该方法包括从处理元件的寄存器文件组读取基地址值和偏移地址值。 处理元件根据基地址值和偏移地址值确定虚拟地址。 处理元件将虚拟地址转换为物理地址，并基于物理地址访问存储器中的位置。