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    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
    31.
    发明申请
    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 审中-公开
    具有降低闸门泄漏电流的更换门

    公开(公告)号：US20130260549A1

    公开(公告)日：2013-10-03

    申请号：US13771937

    申请日：2013-02-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

    IPC: H01L21/285

    CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

    Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。

    RRAM STRUCTURES IN THE BEOL
    36.
    发明申请
    RRAM STRUCTURES IN THE BEOL 有权

    公开(公告)号：US20210280638A1

    公开(公告)日：2021-09-09

    申请号：US16813166

    申请日：2020-03-09

    Applicant: International Business Machines Corporation

    Inventor： Baozhen Li ,  Chih-Chao Yang ,  Barry Linder ,  Vijay Narayanan

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages
    38.
    发明授权
    Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages 有权

    公开(公告)号：US10985075B2

    公开(公告)日：2021-04-20

    申请号：US16157325

    申请日：2018-10-11

    Applicant: International Business Machines Corporation

    Inventor： Ruqiang Bao ,  Unoh Kwon ,  Vijay Narayanan

    IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

    Abstract: Embodiments of the invention are directed to a method that includes forming a first channel fin in an n-type region of a substrate, forming a second channel fin in a p-type region of the substrate, and depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric, the first fin in the n-type region, and the second fin in the p-type region. The work function metal stack over the gate dielectric and the first fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes at least one shared layer of work function metal that is shared with the second work function metal stack.

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