公开(公告)号：US12034066B2

公开(公告)日：2024-07-09

申请号：US18112249

申请日：2023-02-21

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7397 ,  H01L21/0337 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/4238

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

公开(公告)号：US20230207673A1

公开(公告)日：2023-06-29

申请号：US18112249

申请日：2023-02-21

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0649 ,  H01L29/0615 ,  H01L29/7396 ,  H01L29/407 ,  H01L29/0619 ,  H01L29/0623 ,  H01L21/0337 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/4238

Abstract: A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

公开(公告)号：US11581429B2

公开(公告)日：2023-02-14

申请号：US17350505

申请日：2021-06-17

Applicant: Infineon Technologies AG ,  Infineon Technologies Dresden GmbH & Co. KG

Inventor： Matteo Dainese ,  Alexander Philippou ,  Markus Beninger-Bina ,  Ingo Dirnstorfer ,  Erich Griebl ,  Christian Jaeger ,  Johannes Georg Laven ,  Caspar Leendertz ,  Frank Dieter Pfirsch

IPC: H01L29/00 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor switch includes an active cell region with a drift region, an edge termination region, and IGBT cells within the active cell region. Each IGBT cell includes trenches that extend into the drift region and laterally confine mesas. At least one control trench has a control electrode for controlling the load current. At least one dummy trench has a dummy electrode electrically coupled to the control electrode. At least one further trench has a further trench electrode. At least one active mesa is electrically connected to a first load terminal within the active cell region. Each control trench is arranged adjacent to no more than one active mesa. At least one inactive mesa is adjacent to the dummy trench. A cross-trench structure merges each control trench, dummy trench and further trench to each other. The cross-trench structure overlaps at least partially along a vertical direction with the trenches.

公开(公告)号：US20210043759A1

公开(公告)日：2021-02-11

申请号：US17078620

申请日：2020-10-23

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei ,  Caspar Leendertz ,  Christian Philipp Sandow

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

Abstract: A power semiconductor device includes an active cell region with a drift region of a first conductivity type, a plurality of IGBT cells arranged within the active cell region, each of the IGBT cells includes at least one trench that extends into the drift, an edge termination region surrounding the active cell region, a transition region arranged between the active cell region and the edge termination region, at least some of the IGBT cells are arranged within or extend into the transition region, a barrier region of a second conductivity type, the barrier region is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells and does not extend into the transition region, and a first load terminal and a second load terminal, the power semiconductor device is configured to conduct a load current along a vertical direction between.

公开(公告)号：US10903344B2

公开(公告)日：2021-01-26

申请号：US16430970

申请日：2019-06-04

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10 ,  H01L29/861

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor mesa having source zones arranged along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. The semiconductor device further includes stripe-shaped electrode structures on opposite sides of the semiconductor mesa and separation regions between neighboring ones of the source zones. At least one of the electrode structures includes a gate electrode. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation regions.

公开(公告)号：US10410911B2

公开(公告)日：2019-09-10

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US20190237575A1

公开(公告)日：2019-08-01

申请号：US16263244

申请日：2019-01-31

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Hans-Joachim Schulze ,  Matteo Dainese ,  Elmar Falck ,  Franz-Josef Niedernostheide ,  Manfred Pfaffenlehner

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/402

Abstract: A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

公开(公告)号：US10312258B2

公开(公告)日：2019-06-04

申请号：US15209206

申请日：2016-07-13

Applicant: Infineon Technologies AG

Inventor： Johannes Laven ,  Matteo Dainese ,  Hans-Joachim Schulze

IPC: H01L21/70 ,  H01L27/12 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/762 ,  H01L21/768 ,  H01L49/02 ,  H01L29/06 ,  H01L21/74 ,  H01L23/367 ,  H01L23/528 ,  H01L23/00 ,  H01L27/092

Abstract: A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the first surface in an active area. The device further includes a plurality of cavities in the semiconductor substrate beneath the first surface. The device further includes dielectric support structures between each of the cavities and spaced apart from the first surface. The dielectric support structures support a part of the semiconductor substrate between the active area and the cavities. The dielectric support structures include an oxide.

公开(公告)号：US09876100B2

公开(公告)日：2018-01-23

申请号：US14963456

申请日：2015-12-09

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Matteo Dainese ,  Peter Lechner ,  Hans-Joachim Schulze ,  Johannes Georg Laven

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/861 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L29/7393 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/8613 ,  H01L2924/13055

Abstract: A semiconductor device includes a semiconductor mesa having source zones separated from each other along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa, at least one of which includes a gate electrode configured to control a charge carrier flow through the at least one body zone. First portions of the at least one body zone are formed between the source zones and separation regions. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

公开(公告)号：US09536999B2

公开(公告)日：2017-01-03

申请号：US14479460

申请日：2014-09-08

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Hans-Joachim Schulze ,  Matteo Dainese ,  Peter Lechner ,  Roman Baburske

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/0243 ,  H01L21/02658 ,  H01L21/02664 ,  H01L23/544 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/8613 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A semiconductor device includes transistor cells with source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. Control structures include first portions extending into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions in a distance to the first surface between the first portions, and third portions in a distance to the first surface and connecting the first and the second portions, wherein constricted sections of the semiconductor mesa are formed between neighboring third portions.

Abstract translation: 半导体器件包括具有第一导电类型的源区和第二导电类型的体区的晶体管单元。 源区和体区形成在由半导体本体的一部分形成的半导体台面中。 控制结构包括在半导体台面的至少两个相对侧上延伸到半导体本体中的第一部分，在第一部分之间与第一表面有一定距离的第二部分和与第一表面一定距离的第三部分，并且连接第一和 第二部分，其中半导体台面的收缩部分形成在相邻的第三部分之间。