Sandwich-molded cores for high-inductance architectures

    公开(公告)号:US11622448B2

    公开(公告)日:2023-04-04

    申请号:US16505403

    申请日:2019-07-08

    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

    PATCH PACKAGING ARCHITECTURE IMPLEMENTING HYBRID BONDS AND SELF-ALIGNED TEMPLATE

    公开(公告)号:US20230078099A1

    公开(公告)日:2023-03-16

    申请号:US17473414

    申请日:2021-09-13

    Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.

    ELECTRONIC SUBSTRATE CORE HAVING AN EMBEDDED LASER STOP TO CONTROL DEPTH OF AN ULTRA-DEEP CAVITY

    公开(公告)号:US20220399307A1

    公开(公告)日:2022-12-15

    申请号:US17344681

    申请日:2021-06-10

    Abstract: An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

    ELECTRONIC DEVICE PACKAGE WITH REDUCED THICKNESS VARIATION

    公开(公告)号:US20200312787A1

    公开(公告)日:2020-10-01

    申请号:US16369681

    申请日:2019-03-29

    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

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