公开(公告)号：US20190385959A1

公开(公告)日：2019-12-19

申请号：US16012371

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L21/822 ,  H01L27/04 ,  H01F27/28 ,  H01F27/24

Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US20180281374A1

公开(公告)日：2018-10-04

申请号：US15475157

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Sri Chaitra J. Chavali ,  Siddharth K. Alur ,  Kyu Oh Lee

IPC: B32B37/10 ,  B32B37/06 ,  H05K3/00 ,  H05K1/03

CPC classification number: B32B37/10 ,  B32B37/06 ,  B32B2307/202 ,  B32B2309/02 ,  B32B2457/08 ,  H05K3/0064 ,  H05K3/022 ,  H05K3/4602 ,  H05K2203/0278 ,  H05K2203/068

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.

公开(公告)号：US20180240788A1

公开(公告)日：2018-08-23

申请号：US15755533

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： Daniel Sobieski ,  Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Merve Celikkol ,  Kyu Oh Lee ,  Kemal Aygun ,  Zhiguo Qian

IPC: H01L25/18 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

公开(公告)号：US20180076161A1

公开(公告)日：2018-03-15

申请号：US15267065

申请日：2016-09-15

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Amanda E. Schuckman ,  Steve S. Cho

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/16157 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

公开(公告)号：US12224264B2

公开(公告)日：2025-02-11

申请号：US18385167

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US11557489B2

公开(公告)日：2023-01-17

申请号：US16113109

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Sai Vadlamani ,  Junnan Zhao ,  Ji Yong Park ,  Kyu Oh Lee ,  Cheng Xu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

公开(公告)号：US11410921B2

公开(公告)日：2022-08-09

申请号：US16107920

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu Oh Lee

IPC: H01L23/498 ,  H01G4/33 ,  H01L21/48 ,  H01G4/228

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.

公开(公告)号：US20220230800A1

公开(公告)日：2022-07-21

申请号：US17713662

申请日：2022-04-05

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Venkata Ramanuja Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

公开(公告)号：US11380609B2

公开(公告)日：2022-07-05

申请号：US15985348

申请日：2018-05-21

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Jiwei Sun ,  Ji Yong Park ,  Kyu Oh Lee ,  Yikang Deng ,  Zhichao Zhang ,  Liwei Cheng ,  Andrew James Brown

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

公开(公告)号：US11322290B2

公开(公告)日：2022-05-03

申请号：US16012259

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Yikang Deng ,  Kyu Oh Lee ,  Ji Yong Park ,  Srinivas Pietambaram ,  Ying Wang ,  Chong Zhang ,  Rui Zhang ,  Junnan Zhao

IPC: H01F27/28 ,  H01F27/24 ,  H04B5/00 ,  H01F41/04 ,  H01L23/522 ,  H01L49/02 ,  H01L21/822

Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.