公开(公告)号：US11721765B2

公开(公告)日：2023-08-08

申请号：US17499908

申请日：2021-10-13

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Tomoyuki Ito ,  Toshihide Jinnai ,  Isao Suzumura ,  Akihiro Hanada ,  Ryo Onodera

IPC: H01L21/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66 ,  G02F1/1368

CPC classification number: H01L29/78627 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/426 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78633 ,  H01L29/78675 ,  G02F1/1368 ,  H01L2029/42388

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US11630361B2

公开(公告)日：2023-04-18

申请号：US17471881

申请日：2021-09-10

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Toshihide Jinnai ,  Isao Suzumura ,  Hajime Watakabe ,  Ryo Onodera

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L29/786

Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

公开(公告)号：US11442515B2

公开(公告)日：2022-09-13

申请号：US17034722

申请日：2020-09-28

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Hajime Watakabe ,  Kazufumi Watabe

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  G06F1/26 ,  H02J13/00 ,  H04L41/069 ,  H04L47/2416 ,  H04L67/12 ,  H04Q9/02

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

公开(公告)号：US11181792B2

公开(公告)日：2021-11-23

申请号：US16787054

申请日：2020-02-11

Applicant: Japan Display Inc.

Inventor： Toshihide Jinnai ,  Hajime Watakabe ,  Akihiro Hanada ,  Ryo Onodera ,  Isao Suzumura

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  H01L27/32

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.

公开(公告)号：US11003003B2

公开(公告)日：2021-05-11

申请号：US16918453

申请日：2020-07-01

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Isao Suzumura ,  Hajime Watakabe

IPC: G02F1/1333 ,  G02F1/1368 ,  G02F1/1335 ,  G02F1/1362 ,  H01L27/12 ,  G09F9/30 ,  H05K1/18 ,  G02F1/1339 ,  H01L27/32 ,  H01L51/00

Abstract: The purpose of the invention is to realize the flexible display device of high reliability; specifically in a structure that a bending area is in a terminal area, and in that disconnection of the wiring does not occur in the bending area. The concrete structure is that: a display device having a display area, a driving circuit area and a bending area comprising: a first thin film transistor and a first interlayer insulating film are formed in the display area, a second thin film transistor and a second interlayer insulating film are formed in the driving circuit area, terminal wirings to connects the display area and the driving circuit area are formed in the bending area.

公开(公告)号：US10761354B2

公开(公告)日：2020-09-01

申请号：US16153861

申请日：2018-10-08

Applicant: Japan Display Inc.

Inventor： Akihiro Hanada ,  Isao Suzumura ,  Hajime Watakabe

IPC: G02F1/1333 ,  G02F1/1368 ,  G02F1/1335 ,  G02F1/1362 ,  H01L27/12 ,  G09F9/30 ,  H05K1/18 ,  G02F1/1339 ,  H01L27/32 ,  H01L51/00

Abstract: The purpose of the invention is to realize the flexible display device of high reliability; specifically in a structure that a bending area is in a terminal area, and in that disconnection of the wiring does not occur in the bending area. The concrete structure is that: a display device having a display area, a driving circuit area and a bending area comprising: a first thin film transistor and a first interlayer insulating film are formed in the display area, a second thin film transistor and a second interlayer insulating film are formed in the driving circuit area, terminal wirings to connects the display area and the driving circuit area are formed in the bending area.

公开(公告)号：US10727254B2

公开(公告)日：2020-07-28

申请号：US16447000

申请日：2019-06-20

Applicant: Japan Display Inc.

Inventor： Toshinari Sasaki ,  Hajime Watakabe ,  Akihiro Hanada ,  Marina Shiokawa

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.

公开(公告)号：US10373982B2

公开(公告)日：2019-08-06

申请号：US15619677

申请日：2017-06-12

Applicant: Japan Display Inc.

Inventor： Toshinari Sasaki ,  Hajime Watakabe ,  Akihiro Hanada ,  Marina Shiokawa

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.

公开(公告)号：US10317763B2

公开(公告)日：2019-06-11

申请号：US15723300

申请日：2017-10-03

Applicant: Japan Display Inc.

Inventor： Hajime Watakabe ,  Isao Suzumura ,  Hirokazu Watanabe ,  Akihiro Hanada

IPC: H01L29/10 ,  H01L29/12 ,  G02F1/1368 ,  H01L21/8234 ,  H01L21/473 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L29/786 ,  H01L27/12 ,  H01L51/50

Abstract: A display device comprising: a first TFT using silicon (Si) and a second TFT using oxide semiconductor are formed on a substrate, a distance between the silicon (Si) and the substrate is smaller than a distance between the oxide semiconductor and the substrate, a source/drain electrode of the first TFT connects with the silicon (Si) via a first through hole, a source/drain electrode of the second TFT connects with the oxide semiconductor via a second through hole, metal films are made on the oxide semiconductor sandwiching a channel of the oxide semiconductor in a plan view, the channel has a channel width, an AlO layer is formed on the metal films and the oxide semiconductor, the second source/drain electrode and the metal films are connected via the second through hole formed in the AlO layer.

公开(公告)号：US20170365624A1

公开(公告)日：2017-12-21

申请号：US15619677

申请日：2017-06-12

Applicant: Japan Display Inc.

Inventor： Toshinari Sasaki ,  Hajime Watakabe ,  Akihiro Hanada ,  Marina Shiokawa

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/7869

Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.