公开(公告)号：US20080083941A1

公开(公告)日：2008-04-10

申请号：US11538982

申请日：2006-10-05

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1207 ,  H01L29/78

摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.

摘要翻译： 公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。 一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。 该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。 在一个实施例中，带是硅化物带。

公开(公告)号：US08779511B2

公开(公告)日：2014-07-15

申请号：US13530887

申请日：2012-06-22

申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/088

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

公开(公告)号：US07223669B2

公开(公告)日：2007-05-29

申请号：US10710061

申请日：2004-06-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L21/20

CPC分类号： H01L21/3081 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.

摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。

公开(公告)号：US09059000B2

公开(公告)日：2015-06-16

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  G03F7/11

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20080160713A1

公开(公告)日：2008-07-03

申请号：US11617960

申请日：2006-12-29

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L21/28

CPC分类号： H01L27/1203 ,  H01L27/0733 ,  H01L27/1207 ,  H01L29/945

摘要： A method patterns a trench mask over both SOI regions and bulk silicon regions of a single substrate. Next, the SOI regions and the bulk silicon regions are simultaneously etched through the trench mask to form trenches in the SOI regions and the bulk silicon regions. In such processing the buried insulating layer in SOI regions causes trenches within the SOI regions to be less deep (more shallow) than trenches in the bulk silicon regions (which are deeper or less shallow). After the trenches are formed, the method completes the process by forming capacitors in the trenches. More specifically, the method simultaneously lines all of the trenches with an insulator and simultaneously fills all of the trenches with a conductor to form capacitors in the trenches. The capacitors within the SOI regions have a lower capacitance that the capacitors within the SOI regions.

摘要翻译： 一种方法在单个衬底的SOI区域和体硅区域上形成沟槽掩模。 接下来，通过沟槽掩模同时蚀刻SOI区域和体硅区域，以在SOI区域和体硅区域中形成沟槽。 在这种处理中，SOI区域中的掩埋绝缘层使得SOI区域内的沟槽比体硅区域（更深或更浅）中的沟槽更深（更浅）。 在沟槽形成之后，该方法通过在沟槽中形成电容器来完成该工艺。 更具体地，该方法同时用绝缘体对所有沟槽进行排列，同时用导体填充所有沟槽，以在沟槽中形成电容器。 SOI区域内的电容器具有较低的电容，即SOI区域内的电容器。

公开(公告)号：US07132324B2

公开(公告)日：2006-11-07

申请号：US10905002

申请日：2004-12-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

公开(公告)号：US06943409B1

公开(公告)日：2005-09-13

申请号：US10709699

申请日：2004-05-24

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L29/76

CPC分类号： B82Y20/00 ,  H01L27/1446 ,  H01L31/03529 ,  H01L31/105 ,  H01L31/1804 ,  Y02E10/547

摘要： A semiconductor device is formed in on a semiconductor substrate starting with a first step, which is to form a wide trench and a narrow trench in the substrate. Then form a first electrode in the narrow trench by depositing a first fill material of a first conductivity type over the device to fill the wide trench partially and to fill the narrow trench completely. Etch back the first fill material until completion of removal thereof from the wide trench. Form a second electrode in the wide trench by filling the wide trench with a second fill material of an opposite conductivity type. Anneal to drive dopant both from the first fill material of the first electrode into a first outdiffusion region in the substrate about the periphery of the narrow trench and from the second fill material of the second electrode into a second outdiffusion region in the substrate about the periphery of the wide trench.

摘要翻译： 半导体器件形成在半导体衬底上，从第一步骤开始，其在衬底中形成宽沟槽和窄沟槽。 然后通过在器件上沉积第一导电类型的第一填充材料，以便部分填充宽沟槽并完全填充窄沟槽，在窄沟槽中形成第一电极。 将第一填充材料回扫，直到完成从宽沟槽中移除。 通过用相反导电类型的第二填充材料填充宽沟槽在宽沟槽中形成第二电极。 退火以将掺杂剂从第一电极的第一填充材料驱动到衬底周围的窄沟槽的第一外扩散区域中，并且从第二电极的第二填充材料移动到衬底周围的第二外扩散区域 的宽沟。

公开(公告)号：US08236634B1

公开(公告)日：2012-08-07

申请号：US13050023

申请日：2011-03-17

申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/088

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。

公开(公告)号：US20080261128A1

公开(公告)日：2008-10-23

申请号：US12106586

申请日：2008-04-21

申请人： Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

发明人： Deok-kee Kim ,  Kenneth T. Settlemyer ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Thimothy Dalton ,  Katherina Babich ,  Arpan P. Mahorowala ,  Harald Okorn-Schmidt

IPC分类号： G03F7/004 ,  G03F7/20

CPC分类号： H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

摘要翻译： 增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。 提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。 这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

公开(公告)号：US20120261756A1

公开(公告)日：2012-10-18

申请号：US13530887

申请日：2012-06-22

申请人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

发明人： Narasimhulu Kanike ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens

IPC分类号： H01L27/12

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： Thin semiconductor regions and thick semiconductor regions are formed oven an insulator layer. Thick semiconductor regions include at least one semiconductor fin. A gate conductor layer is patterned to form disposable planar gate electrodes over ETSOI regions and disposable side gate electrodes on sidewalls of semiconductor fins. End portions of the semiconductor fins are vertically recessed to provide thinned fin portions adjacent to an unthinned fin center portion. After appropriate masking by dielectric layers, selective epitaxy is performed on planar source and drain regions of ETSOI field effect transistors (FETs) to form raised source and drain regions. Further, fin source and drain regions are grown on the thinned fin portions. Source and drain regions, fins, and the disposable gate electrodes are planarized. The disposable gate electrodes are replaced with metal gate electrodes. FinFETs and ETSOI FETs are provided on the same semiconductor substrate.

摘要翻译： 薄半导体区域和厚半导体区域被形成为绝缘体层。 厚半导体区域包括至少一个半导体鳍片。 图案化栅极导体层以在半导体鳍片的侧壁上的ETSOI区域和一次侧栅电极上形成一次性平面栅电极。 半导体翅片的端部垂直凹入，以提供与未固定的翅片中心部分相邻的变薄的翅片部分。 在通过介电层适当掩蔽之后，在ETSOI场效应晶体管（FET）的平面源极和漏极区域上进行选择性外延以形成升高的源极和漏极区域。 此外，翅片源极和漏极区域在薄的鳍部上生长。 源极和漏极区域，鳍片和一次性栅电极被平坦化。 一次性栅电极被金属栅电极代替。 FinFET和ETSOI FET设置在相同的半导体衬底上。