公开(公告)号：US20150054176A1

公开(公告)日：2015-02-26

申请号：US14503498

申请日：2014-10-01

Applicant: Jae-Hwang Sim ,  Jinhyun Shin

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531

Abstract: Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.

Abstract translation: 提供制造半导体器件的方法包括执行两个光刻工艺和两个间隔工艺，使得图案形成为具有小于光刻工艺限制的间距。 此外，通过执行一次光刻工艺同时限定线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。 还提供了相关设备。

公开(公告)号：US08772855B2

公开(公告)日：2014-07-08

申请号：US12882436

申请日：2010-09-15

Applicant: Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

Inventor： Yoonmoon Park ,  Keonsoo Kim ,  Jinhyun Shin ,  Jae-Hwang Sim

IPC: H01L29/788

CPC classification number: H01L27/11531 ,  H01L27/11526 ,  H01L28/20 ,  H01L28/24

Abstract: Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively.

Abstract translation: 提供了包括电阻器的半导体器件及其制造方法的实施例。 半导体器件包括设置在半导体衬底上以限定沟槽的模具图案，包括主体区域和第一和第二接触区域的电阻图案，其中主体区域覆盖沟槽的底部和侧壁，第一和第二接触区域 分别从模具图案的上表面上的身体区域延伸出来; 以及分别与第一和第二接触区域接触的第一和第二线路。

公开(公告)号：US08754464B2

公开(公告)日：2014-06-17

申请号：US13468552

申请日：2012-05-10

Applicant: Jae-Hwang Sim

Inventor： Jae-Hwang Sim

IPC: H01L29/76 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/7881

Abstract: Non-volatile memory devices and methods of manufacturing the same are disclosed. In a non-volatile memory device, widths of a metal gate and an upper portion of a base gate in a gate electrode are less than the width of a hard mask pattern disposed on the metal gate. First and second protection spacers are disposed on opposing sidewalls of the metal gate and on opposing sidewalls of the upper portion of the base gate, respectively.

Abstract translation: 公开了非易失性存储器件及其制造方法。 在非易失性存储器件中，栅电极中的金属栅极和基极栅极的上部的宽度小于设置在金属栅极上的硬掩模图案的宽度。 第一和第二保护间隔物分别设置在金属栅极的相对的侧壁和基栅的上部的相对侧壁上。

公开(公告)号：US08697580B2

公开(公告)日：2014-04-15

申请号：US13678930

申请日：2012-11-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08519484B2

公开(公告)日：2013-08-27

申请号：US13368556

申请日：2012-02-08

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/70

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US08283248B2

公开(公告)日：2012-10-09

申请号：US13234558

申请日：2011-09-16

Applicant: Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

Inventor： Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

IPC: H01L21/4763

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Abstract translation: 一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

公开(公告)号：US20120064710A1

公开(公告)日：2012-03-15

申请号：US13230228

申请日：2011-09-12

Applicant: Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

Inventor： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

IPC: H01L21/28

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

公开(公告)号：US08129238B2

公开(公告)日：2012-03-06

申请号：US12951490

申请日：2010-11-22

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/8242

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US20110165757A1

公开(公告)日：2011-07-07

申请号：US12951490

申请日：2010-11-22

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US20110115093A1

公开(公告)日：2011-05-19

申请号：US12950347

申请日：2010-11-19

Applicant: Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

Inventor： Yoonmoon PARK ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

IPC: H01L23/528

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿过芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。