公开(公告)号：US20100096719A1

公开(公告)日：2010-04-22

申请号：US12418023

申请日：2009-04-03

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/544

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。 间隔件形成在第一和第二掩模结构的相对侧壁上。 使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间​​选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物 以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。 可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征 。

公开(公告)号：US07611948B2

公开(公告)日：2009-11-03

申请号：US11945477

申请日：2007-11-27

Applicant: Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

Inventor： Jae-Hwang Sim ,  Yong-Sik Yim ,  Ki-Nam Kim ,  Jae-Kwan Park

IPC: H01L21/8247 ,  H01L21/8222

CPC classification number: H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/954

Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.

Abstract translation: 形成非易失性存储器件的方法包括形成第一掩模图案，它们之间的距离可以相对较大。 形成保形地覆盖第一掩模图案的距离调节层。 在第一掩模图案之间的距离调节层的凹槽中形成第二掩模图案。

公开(公告)号：US20080227258A1

公开(公告)日：2008-09-18

申请号：US12074992

申请日：2008-03-07

Applicant: Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Sung-Hyun Kwon ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Jae-Kwan Park

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L27/11521 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11524 ,  H01L27/11568

Abstract: Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer.

Abstract translation: 形成半导体器件的方法包括在半导体衬底上形成掩模层。 掩模层具有垂直和水平延伸的部分。 垂直延伸部分具有选择的厚度，以使要使用掩模层形成的下层结构和高于水平延伸部分的高度的高度提供期望的线宽。 使用掩模层形成底层结构。

公开(公告)号：US09761603B2

公开(公告)日：2017-09-12

申请号：US14964624

申请日：2015-12-10

Applicant: Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

Inventor： Min-Sung Song ,  Jae-Hwang Sim ,  Joon-Sung Lim

IPC: H01L21/4763 ,  H01L27/11573 ,  H01L21/311 ,  H01L27/11526 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/11526

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

公开(公告)号：US08754464B2

公开(公告)日：2014-06-17

申请号：US13468552

申请日：2012-05-10

Applicant: Jae-Hwang Sim

Inventor： Jae-Hwang Sim

IPC: H01L29/76 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L21/764 ,  H01L27/11529 ,  H01L29/42324 ,  H01L29/7881

Abstract: Non-volatile memory devices and methods of manufacturing the same are disclosed. In a non-volatile memory device, widths of a metal gate and an upper portion of a base gate in a gate electrode are less than the width of a hard mask pattern disposed on the metal gate. First and second protection spacers are disposed on opposing sidewalls of the metal gate and on opposing sidewalls of the upper portion of the base gate, respectively.

Abstract translation: 公开了非易失性存储器件及其制造方法。 在非易失性存储器件中，栅电极中的金属栅极和基极栅极的上部的宽度小于设置在金属栅极上的硬掩模图案的宽度。 第一和第二保护间隔物分别设置在金属栅极的相对的侧壁和基栅的上部的相对侧壁上。

公开(公告)号：US08697580B2

公开(公告)日：2014-04-15

申请号：US13678930

申请日：2012-11-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08519484B2

公开(公告)日：2013-08-27

申请号：US13368556

申请日：2012-02-08

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/70

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

公开(公告)号：US08283248B2

公开(公告)日：2012-10-09

申请号：US13234558

申请日：2011-09-16

Applicant: Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

Inventor： Tae-Hyun Kim ,  Kyung-Hyun Kim ,  Jae-Hwang Sim ,  Jae-Jin Shin ,  Jong-Heun Lim ,  Hyun-Min Park

IPC: H01L21/4763

CPC classification number: H01L27/11526 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11573

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.

Abstract translation: 一种制造半导体器件的方法包括：形成多个初步栅极结构，在多个预选栅极结构的侧壁上形成覆盖层图案，以及在多个预选栅极结构的顶表面上形成阻挡层，并且覆盖层 使得它们之间形成空隙。 该方法还包括去除阻挡层和覆盖层图案的上部，使得至少多个预选栅极结构的上侧壁被暴露，并且覆盖层图案的下部保留在预备的栅极结构的下侧壁上 门结构。 所述方法还包括在所述多个预选择门结构的至少上侧壁上形成导电层，使所述导电层与所述预选栅极结构反应，以及在其中形成具有气隙的绝缘层。

公开(公告)号：US20120064710A1

公开(公告)日：2012-03-15

申请号：US13230228

申请日：2011-09-12

Applicant: Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

Inventor： Jae-Hwang Sim ,  Keon-Soo Kim ,  Kyung-Hoon Min ,  Min-Sung Song ,  Yeon-Wook Jung

IPC: H01L21/28

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract translation: 在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。 在基板的有源区上形成第一电介质图案。 导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。 保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。 保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

公开(公告)号：US08129238B2

公开(公告)日：2012-03-06

申请号：US12951490

申请日：2010-11-22

Applicant: Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

Inventor： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

IPC: H01L21/8242

CPC classification number: H01L21/76229

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract translation: 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。