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    Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing
    31.
    发明授权
    Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
    集成电路器件隔离方法采用高选择性化学机械抛光

    公开(公告)号：US06537914B1

    公开(公告)日：2003-03-25

    申请号：US09570225

    申请日：2000-05-12

    申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

    发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

    IPC分类号： H01L21302

    CPC分类号： C09G1/02 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/76224

    摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

    摘要翻译： 用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。 特别地，蚀刻衬底表面以形成沟槽。 然后在衬底表面和沟槽中形成绝缘层。 绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。 包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。 结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

    Semiconductor device including dummy gate part and method of fabricating the same
    32.
    发明申请
    Semiconductor device including dummy gate part and method of fabricating the same 有权
    半导体器件包括伪栅极部分及其制造方法

    公开(公告)号：US20090121296A1

    公开(公告)日：2009-05-14

    申请号：US12291211

    申请日：2008-11-07

    申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    IPC分类号： H01L27/10

    CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

    摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

    Method of Fabricating Semiconductor Device
    33.
    发明申请
    Method of Fabricating Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20080045019A1

    公开(公告)日：2008-02-21

    申请号：US11833050

    申请日：2007-08-02

    申请人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

    发明人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

    IPC分类号： H01L21/302

    CPC分类号： H01L29/66795 ,  H01L29/7851

    摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

    摘要翻译： 公开了一种制造包括多栅极晶体管的半导体器件的方法。 制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。

    Multi-level transistor and related method
    34.
    发明申请
    Multi-level transistor and related method 有权
    多级晶体管及相关方法

    公开(公告)号：US20070045671A1

    公开(公告)日：2007-03-01

    申请号：US11485485

    申请日：2006-07-13

    申请人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

    发明人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

    IPC分类号： H01L29/768

    CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/12

    摘要： A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.

    摘要翻译： 公开了一种包括具有单晶特性的第二有源区和多电平晶体管的制造方法的多电平晶体管。 所述多电平晶体管包括衬底，所述衬底包括第一有源区，形成在所述第一有源区上的第一晶体管，覆盖所述第一晶体管的第一绝缘层，并且适于隔离所述第一有源区;第二有源区， 形成在第一绝缘层上的选择性外延生长（SEG）层和形成在第二有源区上的第二晶体管。

    Method for fabricating MOS transistor using selective silicide process
    37.
    发明授权
    Method for fabricating MOS transistor using selective silicide process 有权
    使用选择性硅化物工艺制造MOS晶体管的方法

    公开(公告)号：US06383882B1

    公开(公告)日：2002-05-07

    申请号：US09860591

    申请日：2001-05-21

    申请人： Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

    发明人： Sun-wung Lee ,  Jae-phil Boo ,  Kyung-hyun Kim ,  Chang-ki Hong

    IPC分类号： H01L21336

    CPC分类号： H01L21/823468 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823443

    摘要： A method for fabricating a MOS transistor using a selective silicide process wherein a gate insulating layer and a gate polysilicon layer are sequentially formed on a silicon substrate, and a gate spacer is formed on a side wall of the gate insulating layer and the gate polysilicon layer. Impurity ions are implanted and diffused using the gate spacer and the gate polysilicon layer as a mask layer to form a source/drain region in the substrate. An etching blocking layer is formed to cover the source/drain region, the gate spacer, and the gate polysilicon layer, and then, a dielectric layer to cover the etching blocking layer is formed. The dielectric layer is planarized, and the etching blocking layer on the gate polysilicon layer is exposed. The exposed etching blocking layer and a part of the gate spacer are etched, and a top surface and a top side of the gate polysilicon layer are exposed. A silicide layer is formed over the exposed part of the gate polysilicon layer.

    摘要翻译： 一种使用选择性硅化物工艺制造MOS晶体管的方法，其中在硅衬底上依次形成栅极绝缘层和栅极多晶硅层，并且栅极间隔物形成在栅极绝缘层和栅极多晶硅层的侧壁上 。 使用栅极间隔物和栅极多晶硅层作为掩模层注入和扩散杂质离子，以在衬底中形成源极/漏极区域。 形成蚀刻阻挡层以覆盖源极/漏极区域，栅极间隔物和栅极多晶硅层，然后形成覆盖蚀刻阻挡层的电介质层。 介电层被平坦化，并且露出栅极多晶硅层上的蚀刻阻挡层。 蚀刻暴露的蚀刻阻挡层和栅极间隔物的一部分，并且露出栅极多晶硅层的顶表面和顶侧。 在栅极多晶硅层的暴露部分上形成硅化物层。

    Chemical mechanical polishing method using double polishing stop layer
    38.
    发明授权
    Chemical mechanical polishing method using double polishing stop layer 失效
    化学机械抛光方法采用双抛光停止层

    公开(公告)号：US06248667B1

    公开(公告)日：2001-06-19

    申请号：US09527458

    申请日：2000-03-17

    申请人： Jung-yup Kim ,  Chang-ki Hong

    发明人： Jung-yup Kim ,  Chang-ki Hong

    IPC分类号： H01L21302

    CPC分类号： H01L21/31053 ,  H01L21/318 ,  H01L21/3185 ,  Y10S438/959

    摘要： A chemical mechanical polishing (CMP) method using a double polishing stopper by which it is possible to prevent a dishing phenomenon and a variation in the thickness of a polishing stopper, including the steps of stacking polishing stoppers to form the double polishing stopper on a semiconductor substrate, forming a trench, stacking an isolation layer, performing a first CMP process using a second polishing stopper, removing the second polishing stopper, and performing a second CMP process using a first polishing stopper. It is possible to remove the second polishing stopper by additionally interposing an etching stopper between the polishing stoppers which form the double polishing stopper.

    摘要翻译： 一种使用双重抛光止动器的化学机械抛光（CMP）方法，其可以防止抛光停止的凹陷现象和厚度的变化，包括堆叠抛光阻挡件以在半导体上形成双重抛光阻挡件的步骤 衬底，形成沟槽，堆叠隔离层，使用第二抛光止挡件执行第一CMP处理，去除第二抛光阻挡件，以及使用第一抛光停止件进行第二CMP处理。 通过在形成双重抛光止动件的抛光止动器之间附加插入蚀刻止动件可以移除第二抛光止动件。

    Wire forming method for semiconductor device
    39.
    发明授权
    Wire forming method for semiconductor device 失效
    半导体器件的成线方法

    公开(公告)号：US5604156A

    公开(公告)日：1997-02-18

    申请号：US560913

    申请日：1995-11-20

    申请人： U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    发明人： U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002

    摘要： A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.

    摘要翻译： 一种用于半导体器件的线形成方法包括以下步骤：在半导体衬底上沉积绝缘材料并图案化绝缘材料以形成第一绝缘层，在第一绝缘层上形成下覆盖层，蚀刻下封盖层和 第一绝缘层以形成暴露半导体衬底的第一部分的第一接触孔，在覆盖层和半导体衬底的第一部分上方形成引线层，对相对于第二绝缘层进行化学和机械抛光（CMP）处理 线层和下覆盖层以暴露第一绝缘层，在导线层和第一绝缘层上形成第二绝缘层，并蚀刻第一和第二绝缘层以形成第二接触孔，其暴露第二绝缘层的第二部分 半导体衬底。 线形成方法可以防止线层的提升，下绝缘层的分离，以及在第二接触孔处形成突起。