公开(公告)号：US09298662B2

公开(公告)日：2016-03-29

申请号：US12633441

申请日：2009-12-08

Applicant: Keith M. Campbell ,  Patrick L. Caporale ,  Caroline M. Metry ,  Pravin Patel

Inventor： Keith M. Campbell ,  Patrick L. Caporale ,  Caroline M. Metry ,  Pravin Patel

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/409

Abstract: Settings are provided by a chassis management controller to an expansion card in a multi-slot server chassis. The chassis management controller in a multi-slot server chassis provides an operating parameter to a server management controller in a server, and the server management controller writes the operating parameter to a port expander of an expansion card installed on the server. The operating parameter is written to the port expander prior to expansion card power up, and the expansion card uses the operating parameter after power up to derive one or more SERDES value. The SERDES value is used to program an ASIC chip comprising a SERDES converter on the expansion card. In one example, the operating parameter is determined by the capabilities of a chassis midplane at the slot where the compute node is installed.

Abstract translation: 设备由机箱管理控制器提供给多插槽服务器机箱中的扩展卡。 多槽服务器机箱中的机箱管理控制器为服务器中的服务器管理控制器提供操作参数，服务器管理控制器将操作参数写入服务器上安装的扩展卡的端口扩展器。 在扩展卡上电之前，将操作参数写入端口扩展器，上电后扩展卡使用操作参数来导出一个或多个SERDES值。 SERDES值用于在扩展卡上对包含SERDES转换器的ASIC芯片进行编程。 在一个示例中，操作参数由安装计算节点的插槽处的机箱中面板的能力确定。

公开(公告)号：US20130327378A1

公开(公告)日：2013-12-12

申请号：US13491390

申请日：2012-06-07

Applicant: Pravin Patel ,  Benjamin Cho

Inventor： Pravin Patel ,  Benjamin Cho

IPC: H01L31/0725

CPC classification number: H01L31/06875 ,  Y02E10/544

Abstract: A multijunction solar cell including a first solar subcell having a first band gap and a first short-circuit current; a second solar subcell disposed over the first solar subcell and having a second band gap greater than the first band gap and a second short-circuit current greater than the first short-circuit current by an amount in the range of 2% to 6%; a third solar subcell disposed over the second solar subcell and having a third band gap greater than the second band gap and a third short-circuit current less than the first short-circuit current by an amount in the range of 2% to 6%; and a fourth solar subcell disposed over the third solar subcell having a fourth band gap greater than the third band gap, and a fourth short-circuit current less than the third short-circuit current by an amount in the range of 6% to 10%, so that at an “end of life” state of the multijunction solar cell in an AM0 space environment the short-circuit current of each of the subcells are substantially identical.

Abstract translation: 一种多结太阳能电池，包括具有第一带隙和第一短路电流的第一太阳能子电池; 第二太阳能子电池，设置在所述第一太阳能子电池上，并且具有大于所述第一带隙的第二带隙和大于所述第一短路电流的第二短路电流，所述第二短路电流的量在2％至6％的范围内; 设置在所述第二太阳能子电池上方的第三太阳能子电池，并且具有大于所述第二带隙的第三带隙和小于所述第一短路电流的第二短路电流，所述第三短路电流的量在2％至6％的范围内; 以及设置在所述第三太阳能子电池上的第四太阳能子电池，其具有大于所述第三带隙的第四带隙，以及小于所述第三短路电流的第四短路电流的范围为6％至10％ ，使得在AM0空间环境中的多结太阳能电池的“寿命终止”状态下，每个子电池的短路电流基本相同。

公开(公告)号：US20120285519A1

公开(公告)日：2012-11-15

申请号：US13104451

申请日：2011-05-10

Applicant: Richard W. Hoffman, JR. ,  Pravin Patel ,  Tansen Varghese

Inventor： Richard W. Hoffman, JR. ,  Pravin Patel ,  Tansen Varghese

IPC: H01L31/06

CPC classification number: H01L31/078 ,  H01L31/022425 ,  H01L31/022433 ,  H01L31/0693 ,  Y02E10/544 ,  Y02P70/521

Abstract: A photovoltaic solar cell for producing energy from the sun including a germanium substrate including a first photoactive junction and forming a bottom solar subcell; a gallium arsenide middle cell disposed on said substrate; an indium gallium phosphide top cell disposed over the middle cell; and a surface grid including a plurality of spaced apart grid lines, wherein the grid lines have a thickness greater than 7 microns, and each grid line has a cross-section in the shape of a trapezoid with a cross-sectional area between 45 and 55 square microns.

Abstract translation: 一种用于从太阳生成能量的光伏太阳能电池，其包括包含第一光活性连接点并形成底部太阳能子电池的锗衬底; 设置在所述衬底上的砷化镓中间电池; 设置在中间电池上方的磷化铟镓顶电池; 以及包括多个间隔开的网格线的表面网格，其中网格线具有大于7微米的厚度，并且每个网格线具有梯形形状的横截面，横截面积在45和55之间 平方微米。

公开(公告)号：US20100117614A1

公开(公告)日：2010-05-13

申请号：US12270477

申请日：2008-11-13

Applicant: Justin P. Bandholz ,  Nickolas J. Gruendler ,  Pravin Patel

Inventor： Justin P. Bandholz ,  Nickolas J. Gruendler ,  Pravin Patel

IPC: G05F1/56

CPC classification number: H02M3/156

Abstract: Tuning a switching power supply, the power supply including a switching transistor; a filter circuit; a pulse generator that drives the switching transistor; a programmable filter connected to the output of the filter circuit; a digital signal processor (‘DSP’) connected to the output of the filter circuit, the DSP configured to program the programmable filter; and a tuning control circuit connected to the output of the filter circuit, to the pulse generator, and to the DSP; including calculating by the DSP, from sampled voltage values of a tuning pulse driven through the filter circuit by the pulse generator, the actual impedance of the filter circuit; and programming, by the DSP, the programmable filter, setting the combined impedance of the filter circuit and the programmable filter to the design impedance of the filter circuit.

Abstract translation: 调谐开关电源，电源包括开关晶体管; 滤波电路; 驱动开关晶体管的脉冲发生器; 连接到滤波电路的输出的可编程滤波器; 数字信号处理器（“DSP”）连接到滤波电路的输出端，DSP配置为对可编程滤波器进行编程; 以及调谐控制电路，连接到滤波电路的输出，脉冲发生器和DSP; 包括由DSP计算的脉冲发生器通过滤波电路驱动的调谐脉冲的采样电压值，滤波器电路的实际阻抗; 并由DSP编程可编程滤波器，将滤波电路和可编程滤波器的组合阻抗设置为滤波电路的设计阻抗。

公开(公告)号：US20080301352A1

公开(公告)日：2008-12-04

申请号：US11757942

申请日：2007-06-04

Applicant: P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

Inventor： P. Maurice Bland ,  Moises Cases ,  Jonathan R. Hinkle ,  Pravin Patel ,  Nam H. Pham

IPC: G06F13/40

CPC classification number: G06F13/4086

Abstract: A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus.

Abstract translation: 一种用于实现总线的系统和方法。 在一个实施例中，系统包括可操作以耦合到总线的总线开关和耦合到总线开关的多个迹线段，其中迹线段具有不同的长度。 总线开关可以根据至少一个系统要求将一个跟踪段连接到总线，并且所选择的跟踪段取消总线上的信号反射。

公开(公告)号：US20080084679A1

公开(公告)日：2008-04-10

申请号：US11539990

申请日：2006-10-10

Applicant: Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

Inventor： Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

IPC: H05K7/00

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09318 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract translation: 公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

公开(公告)号：US20070257699A1

公开(公告)日：2007-11-08

申请号：US11407814

申请日：2006-04-20

Applicant: Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

Inventor： Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

IPC: H03K17/16

CPC classification number: G11C5/04 ,  G11C5/063

Abstract: A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memory modules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around the predetermined location.

Abstract translation: 公开了一种多存储器模块电路拓扑，其包括存储器控制器，通过存储器总线连接到存储器控制器的多个存储器模块，以及以星爆拓扑连接到多个存储器模块的谐振器。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的方法，其包括通过存储器总线提供连接到存储器控制器的多个存储器模块，选择星爆拓扑，并且依次将谐振器连接到多个存储器模块 在选定的星爆拓扑上。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的附加方法，其包括由谐振器在至少两个存储器模块之间的多存储器模块电路中的预定位置处提供预定的不连续性减小阻抗，所述多存储器模块 电路具有围绕预定位置逻辑布置的多个部件。

公开(公告)号：US20070178289A1

公开(公告)日：2007-08-02

申请号：US11340907

申请日：2006-01-27

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

IPC: B32B3/00

CPC classification number: B32B17/04 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09227 ,  Y10T428/24917

Abstract: An electronic system includes a circuit board formed from a composite material. The composite material includes fibers embedded within a substrate and the fibers are oriented substantially orthogonal to one another. A plurality of traces are formed on the board, and the plurality of traces are oriented relative to at least one of the fibers at an angle between about 17.5° and about 27.5° or between about 20.0° and about 25.0°. A pair of the traces are oriented substantially orthogonal to one another, and a pair of the traces are oriented relative to one another at an angle of about 45.0°. The fibers are fiberglass, and the substrate is an epoxy resin. The fibers have a different dielectric constant than the substrate.

Abstract translation: 电子系统包括由复合材料形成的电路板。 复合材料包括嵌入基片内的纤维，纤维彼此基本正交。 在板上形成多个迹线，并且多个迹线相对于至少一个光纤以约17.5°至约27.5°之间的角度或约20.0°至约25.0°的角度定向。 一对迹线基本上彼此正交地定向，并且一对迹线以大约45.0°的角度相对于彼此定向。 纤维是玻璃纤维，基材是环氧树脂。 纤维的介电常数不同于基材。

公开(公告)号：US09277601B2

公开(公告)日：2016-03-01

申请号：US12393614

申请日：2009-02-26

Applicant: Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

Inventor： Justin P. Bandholz ,  Joseph E. Maxwell ,  Pravin Patel ,  Phillip L. Weinstein

IPC: H05B1/02 ,  H05B6/64

CPC classification number: H05B6/6441

Abstract: Method and computer program product for using an RFID antenna of a cooking appliance to read a plurality of cooking instruction sets from a single RFID tag associated with a food product that is positioned to be cooked by the cooking appliance. The cooking appliance selects one of the plurality of cooking instruction sets that the cooking appliance is capable of performing. Furthermore, the cooking appliance may then automatically cook the food product by controlling the cooking appliance according to the selected cooking instruction set. The selection of a cooking instruction set may consider the temperature of the food product or a determination whether the food product is frozen. Alternatively, cooking appliance settings may be interpolated between two cooking instruction sets or calculated on the basis of physical property information about the food product.

Abstract translation: 用于使用烹饪器具的RFID天线的方法和计算机程序产品从与烹饪器具定位烹饪的食品相关联的单个RFID标签读取多个烹饪指令集。 烹饪器具选择烹饪器具能够执行的多个烹饪指令集中的一个。 此外，烹饪器具然后可以根据所选择的烹饪指令集来控制烹饪器具来自动烹饪食品。 烹饪指导集的选择可以考虑食品的温度或者确定食品是否被冷冻。 或者，烹饪器具设置可以在两个烹饪指令集之间插值，或者基于关于食品的物理属性信息来计算。

公开(公告)号：US20120194992A1

公开(公告)日：2012-08-02

申请号：US13439221

申请日：2012-04-04

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: G06F1/16 ,  H05K3/30

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电连接到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。