公开(公告)号：US20120049285A1

公开(公告)日：2012-03-01

申请号：US13184318

申请日：2011-07-15

申请人： Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

发明人： Sung-Woo Hyun ,  Yu-Gyun Shin ,  Sun-Ghil Lee ,  Hong-Sik Yoon

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

摘要翻译： 提供一种制造半导体器件和半导体器件的方法。 该方法包括制造半导体器件的方法，该半导体器件包括提供具有限定在其中的第一半导体器件区域和第二半导体器件区域的半导体衬底，在第一半导体器件区域中形成第一栅极结构，在第二半导体中形成第二栅极结构 形成与所述第一栅极结构的第一侧相邻的第一沟槽，形成邻近所述第二栅极结构的第一侧的第二沟槽，以及在所述第一沟槽中形成第一半导体图案并形成第二半导体图案 第二沟槽，其中第一和第二沟槽彼此具有不同的横截面形状。

公开(公告)号：US07799648B2

公开(公告)日：2010-09-21

申请号：US12478345

申请日：2009-06-04

申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC分类号： H01L21/336

CPC分类号： C30B29/06 ,  C30B15/00

摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

公开(公告)号：US20100072545A1

公开(公告)日：2010-03-25

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹陷。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US07608509B2

公开(公告)日：2009-10-27

申请号：US11494439

申请日：2006-07-27

申请人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Sung-Kweon Baek ,  Young-Jin Noh

发明人： Chul-Sung Kim ,  Yu-Gyun Shin ,  Bon-Young Koo ,  Sung-Kweon Baek ,  Young-Jin Noh

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device. Thus, the semiconductor device may have improved electrical characteristics and reliability.

摘要翻译： 在半导体器件和半导体器件的制造方法中，在衬底上形成具有突出的上部的预备隔离区以限定有源区。 在有源区上形成绝缘层之后，在绝缘层上形成第一导电层。 去除预分离区域的突出的上部，以在衬底上形成隔离区域并暴露第一导电层的侧壁，并且补偿构件形成在绝缘层的边缘部分上。 补偿构件可以补充绝缘层的边缘部分，该边缘部分的厚度基本上比绝缘层的中心部分的厚度更薄，并且可以防止绝缘层的劣化。 此外，具有基本上大于有源区的宽度的第一导电层可以增强半导体器件的耦合比。 因此，半导体器件可以具有改善的电特性和可靠性。

公开(公告)号：US07560319B2

公开(公告)日：2009-07-14

申请号：US11730262

申请日：2007-03-30

申请人： Sung-Kwan Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Yong-Hoon Son

发明人： Sung-Kwan Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Yong-Hoon Son

IPC分类号： H01L21/84

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84

摘要： A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.

摘要翻译： 一种制造半导体器件的方法包括在单晶硅衬底上形成绝缘层结构，通过蚀刻绝缘层结构的一部分形成包括第一开口的第一绝缘层结构图案， 单晶硅层，并且通过将第一激光束照射到非单晶硅层上而形成单晶硅图案。 该方法还包括通过蚀刻第一绝缘层结构的一部分来形成包括第二开口的第二绝缘层结构图案，用非单晶硅锗层填充第二开口，以及形成单晶硅 - 锗图案，通过将第二激光束照射到非单晶硅 - 锗层上。

公开(公告)号：US20090130826A1

公开(公告)日：2009-05-21

申请号：US12330796

申请日：2008-12-09

申请人： Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

发明人： Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer.

摘要翻译： 提供了在硅锗（SiGe）层上形成具有应变硅（Si）层的半导体器件的方法。 该方法包括制备硅衬底。 在硅衬底上形成SiGe层。 至少一部分SiGe层具有第一位错密度。 在SiGe层上形成具有低于第一位错密度的第二位错密度的应变Si层。

公开(公告)号：US07514744B2

公开(公告)日：2009-04-07

申请号：US11322335

申请日：2005-12-30

申请人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

发明人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

摘要翻译： 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。

公开(公告)号：US07422965B2

公开(公告)日：2008-09-09

申请号：US11447436

申请日：2006-06-06

申请人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

发明人： Yong-Hoon Son ,  Yu-Gyun Shin ,  Jong-Wook Lee

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/16

摘要： A method of fabricating a transistor device includes forming a non-crystalline germanium layer on a seed layer. The non-crystalline germanium layer is selectively locally heated to about a melting point thereof to form a single-crystalline germanium layer on the seed layer. The non-crystalline germanium layer may be selectively locally heated, for example, by applying a laser to a portion of the non-crystalline germanium layer. Related devices are also discussed.

摘要翻译： 制造晶体管器件的方法包括在种子层上形成非结晶锗层。 选择性地将非结晶锗层局部加热至其熔点，以在籽晶层上形成单晶锗层。 可以例如通过对非晶锗层的一部分施加激光来选择性地局部加热非晶锗层。 还讨论了相关设备。

公开(公告)号：US20080157095A1

公开(公告)日：2008-07-03

申请号：US12045890

申请日：2008-03-11

申请人： Yong-Hoon Son ,  Yu-Gyun Shin

发明人： Yong-Hoon Son ,  Yu-Gyun Shin

IPC分类号： H01L29/04

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/8221 ,  H01L27/0688

摘要： Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

摘要翻译： 提供具有至少一个单晶硅层的半导体器件的制造方法。 根据这些方法，形成包括硅的第一籽晶层。 然后在第一种子层上形成第一非单晶硅层。 用激光照射第一非单晶硅层，以将第一非单晶硅层转变为第一单晶硅层。 还公开了相应的半导体器件。

公开(公告)号：US20080093674A1

公开(公告)日：2008-04-24

申请号：US11952676

申请日：2007-12-07

申请人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

发明人： Deok-Hyung Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Min-Gu Kang

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.

摘要翻译： 在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。 第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。 在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。 在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。 可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。