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31.发明授权Process for etching an organic dielectric using a silyated photoresist mask 有权使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法公开(公告)号：US06660645B1
公开(公告)日：2003-12-09
申请号：US10051725
申请日：2002-01-17
IPC分类号： H07L21302
CPC分类号： H01L21/31144
摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
摘要翻译： 用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。 使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。 金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。
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公开(公告)号：US06605855B1
公开(公告)日：2003-08-12
申请号：US09650538
申请日：2000-08-30
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L2900
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译： 本发明涉及在绝缘材料层中制造互连线和通孔的方法。 在绝缘材料层中形成通孔。 形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。 执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。 通孔和沟槽填充有导电金属。
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公开(公告)号：US06326231B1
公开(公告)日：2001-12-04
申请号：US09207562
申请日：1998-12-08
申请人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
发明人： Ramkumar Subramanian , Bhanwar Singh , Sanjay K. Yedur , Marina V. Plat , Christopher F. Lyons , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L2100
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/3143 , H01L21/3145
摘要： In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating. In another embodiment, the present invention relates to a method of reducing an apparent reflectivity of a metal layer having a first reflectivity in a semiconductor structure, involing forming a silicon oxynitride antireflection coating over the metal layer; wherein the silicon oxynitride antireflection coating formed over the metal layer has a second reflectivity and is formed by depositing silicon oxynitride on the metal layer by chemical vapor deposition and forming an oxide layer over the oxynitride, and the difference between the first reflectivity and the second reflectivity is at least about 60%.
摘要翻译： 在一个实施方案中，本发明涉及在金属层上形成氮氧化硅抗反射涂层的方法，包括以下步骤：在半导体衬底的至少一部分上提供包括金属层的半导体衬底; 在所述金属层上沉积厚度为约至约的氧氮化硅层; 并在氮氧化硅层上形成厚度约为5-20埃的氧化物层，以提供氮氧化硅抗反射涂层。 在另一个实施方案中，本发明涉及一种在半导体结构中减少具有第一反射率的金属层的表观反射率的方法，包括在金属层上形成氮氧化硅抗反射涂层; 其中形成在所述金属层上的所述氧氮化硅抗反射涂层具有第二反射率，并且通过化学气相沉积在所述金属层上沉积氧氮化硅并在所述氧氮化物上形成氧化物层，并且所述第一反射率和所述第二反射率之间的差异 至少约60％。
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公开(公告)号：US06255202B1
公开(公告)日：2001-07-03
申请号：US09619836
申请日：2000-07-20
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28123 , H01L21/76807 , H01L29/4238 , H01L29/4925
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译： 提供了一种制造T型栅结构的方法。 提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。 形成部分地延伸到绝缘层中的开口。 绝缘层中的开口从绝缘层的顶表面延伸到第一深度。 然后在开口的两侧形成隔板。 然后将开口在绝缘层中从第一深度延伸到第二深度。 开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。 然后将隔离物从开口中取出。 然后用导电材料填充开口以形成T形栅结构。
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公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。
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36.发明授权公开(公告)号：US06753266B1
公开(公告)日：2004-06-22
申请号：US09845654
申请日：2001-04-30
IPC分类号： H01L21309
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828
摘要： An exemplary method of fabricating an integrated circuit can include depositing a reflective metal material layer over a layer of polysilicon, depositing an anti-reflective coating over the reflective metal material layer, trim etching the anti-reflective coating to form a pattern, etching the reflective metal material layer according to the pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of anti-reflective coating.
摘要翻译： 制造集成电路的示例性方法可以包括在多晶硅层上沉积反射金属材料层，在反射金属材料层上沉积抗反射涂层，修整蚀刻抗反射涂层以形成图案，蚀刻反射 金属材料层，并且使用由抗反射涂层的去除部分形成的图案去除多晶硅层的部分。
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37.发明授权Sensor to predict void free films using various grating structures and characterize fill performance 失效传感器预测使用各种光栅结构的无空隙膜，并表征填充性能公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译： 本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。 本发明还涉及其工具表征过程及其系统。
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38.发明授权公开(公告)号：US06605413B1
公开(公告)日：2003-08-12
申请号：US10230171
申请日：2002-08-29
IPC分类号： G03F726
CPC分类号： G03F7/40 , G03F7/2024 , G03F7/405
摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then reacted with a stabilizer agent to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a stabilizer-treated photoresist and a composition for a photoresist that strengthens when exposed to a stabilizer agent.
摘要翻译： 提供了一种用于形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。 光致抗蚀剂层通过掩模曝光并显影。 然后光致抗蚀剂层与稳定剂反应以在光致抗蚀剂层干燥之前改变其材料性质。 还提供了使用稳定剂处理的光致抗蚀剂的半导体制造方法和当暴露于稳定剂时增强的光致抗蚀剂组合物。
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39.发明授权Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer 失效通过退火金属层以形成金属硅化物并且使用金属硅化物作为硬掩模来制造半导体器件以图案化多晶硅层的方法公开(公告)号：US06566214B1
公开(公告)日：2003-05-20
申请号：US10047036
申请日：2002-01-17
IPC分类号： H01L213213
CPC分类号： H01L21/28123
摘要： A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.
摘要翻译： 提供制造半导体器件的方法。 在衬底上形成多晶硅层，并且在多晶硅层上形成金属层。 退火金属层和多晶硅层，以在多晶硅层上形成金属硅化物层。 图案化金属硅化物层，然后使用图案化的金属硅化物层作为掩模来对多晶硅层进行构图。 图案化的金属硅化物和多晶硅层可以用作MOSFET的栅电极。
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40.发明授权Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques 有权具有低k介电材料的互连结构和使用单镶嵌和双镶嵌技术制作相同的方法
公开(公告)号：US06127089A
公开(公告)日：2000-10-03
申请号：US143105
申请日：1998-08-28
IPC分类号： G03F7/075 , H01L21/311 , H01L21/768 , G03C1/76
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76802 , H01L21/76807 , G03F7/075
摘要： A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is a convertible layer that upon exposure to the plasma etch that etches the low k dielectric material, converts the silicon-rich imageble layer into a mask layer containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.
摘要翻译： 一种镶嵌结构及其在低k电介质材料中的制造方法采用其中提供镶嵌图案的可成像层。 可成像层是可转换层，其在暴露于蚀刻低k介电材料的等离子体蚀刻时，例如将富含硅的图像层转换成含有二氧化硅的掩模层。 通过由此产生的掩模来保护低k电介质材料免于进一步蚀刻。
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