中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.021 seconds)

    SEMICONDUCTOR MEMORY DEVICE
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220301615A1

    公开(公告)日：2022-09-22

    申请号：US17472361

    申请日：2021-09-10

    Applicant: Kioxia Corporation

    Inventor： Hiroshi Maejima

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C5/06

    Abstract: According to one embodiment, a semiconductor memory device includes a first bit line extending in a first direction and coupled to a first memory cell, a first pad coupled to the first bit line, a first sense amplifier coupled to the first pad, a second bit line being adjacent to the first bit line and extending in the first direction and coupled to a second memory cell, a second pad coupled to the second bit line, and a second sense amplifier coupled to the second pad. The first and second sense amplifiers are adjacent to each other and are arranged in a second direction intersecting the first direction. The first and second pads are adjacent to each other and are arranged in a third direction intersecting the first direction and the second direction.

    Semiconductor memory device
    33.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12230327B2

    公开(公告)日：2025-02-18

    申请号：US18524458

    申请日：2023-11-30

    Applicant: Kioxia Corporation

    Inventor： Hiroshi Maejima

    IPC: G11C16/28 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/32

    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

    Semiconductor memory device having memory chip bonded to a CMOS chip including a peripheral circuit
    34.
    发明授权
    Semiconductor memory device having memory chip bonded to a CMOS chip including a peripheral circuit 有权

    公开(公告)号：US12211544B2

    公开(公告)日：2025-01-28

    申请号：US18239140

    申请日：2023-08-29

    Applicant: Kioxia Corporation

    Inventor： Hiroshi Maejima

    IPC: G11C7/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C7/18 ,  H10B43/10

    Abstract: A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction. The third sense amplifier belongs to a second sense amplifier group. The first and second sense amplifier groups are adjacent to each other and are arranged in the first direction.

    Semiconductor memory device
    36.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11942153B2

    公开(公告)日：2024-03-26

    申请号：US17552225

    申请日：2021-12-15

    Applicant: Kioxia Corporation

    Inventor： Hiroshi Maejima

    IPC: G11C16/04 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

    CPC classification number: G11C16/0433 ,  G11C7/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

    Abstract: According to one embodiment, a semiconductor memory device includes a first string unit including a first memory string including a first selection transistor and a first memory cell coupled to the first selection transistor, a second string unit including a second memory string including a second selection transistor and a second memory cell coupled to the second selection transistor, a first select gate line, a second select gate line, a first bit line, a second bit line, and a first word line. Both of the first select gate line and the second select gate line are selected in a first read operation. The first select gate line is selected and the second select gate line is not selected in a second read operation.

Patent Agency Ranking