公开(公告)号：US07180121B2

公开(公告)日：2007-02-20

申请号：US11085197

申请日：2005-03-22

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/66825 ,  Y10S257/905

摘要： A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.

摘要翻译： 半导体器件包括：衬底，其包括半导体和沟槽;以及在该衬底上的电可重写半导体存储单元，所述半导体存储单元包括电荷存储层，所述电荷存储层包括上表面和下表面，所述下表面的面积较小 比电荷存储层的下表面和沟槽的底面之间的第一绝缘层设置在沟槽中的电荷存储层的至少一部分，第二绝缘层在侧面 沟槽的表面和电荷存储层的侧表面和沟槽的侧表面与第一绝缘层的侧表面之间，电荷存储层上的第三绝缘层和第三绝缘层上的控制栅极电极 。

公开(公告)号：US20060205233A1

公开(公告)日：2006-09-14

申请号：US11431076

申请日：2006-05-10

申请人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

发明人： Katsuhiko Hieda ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Katsuhiko Tachibana ,  Soichi Yamazaki

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31683 ,  H01L21/76224 ,  H01L21/76229

摘要： There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.

公开(公告)号：US20060134928A1

公开(公告)日：2006-06-22

申请号：US11246145

申请日：2005-10-11

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda

IPC分类号： H01L21/469 ,  B05C5/00

CPC分类号： B05B9/04 ,  B05B9/047 ,  B05C11/08 ,  B05C11/10

摘要： A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.

摘要翻译： 半导体制造装置包括将涂布液排出到基板上的排出部; 气体供给管，将惰性气体供给到容纳所述涂布液的液体容器内，对所述液体容器的内部进行加压; 涂料液体供给管通过来自气体供给管的加压将涂布液从液体容器密封地供给到排出部; 第一连接部分，其能够将液体容器附接到涂布液供应管和从涂布液供应管分离; 第二连接部分，其能够将液体容器附接到气体供应管和从气体供应管排出; 以及将能够溶解涂布液的溶剂供给到第一连接部的溶剂供给管。

公开(公告)号：US06964899B2

公开(公告)日：2005-11-15

申请号：US10997889

申请日：2004-11-29

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L23/48 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device having a bit line extending in a first direction, a plurality of transistors electrically connected to the bit line, a plurality of first electrodes arranged in the first direction and electrically connected to the transistors, a dielectric film covering upper and side surfaces of the first electrodes, and a second electrode covering the dielectric film, wherein a width of the first electrode is smaller than a distance between adjacent first electrodes and smaller than the minimum value of design rule of the semiconductor device.

摘要翻译： 公开了一种具有沿第一方向延伸的位线的半导体器件，与位线电连接的多个晶体管，沿第一方向排列并与晶体管电连接的多个第一电极，覆盖上部和侧部的电介质膜 第一电极的表面和覆盖电介质膜的第二电极，其中第一电极的宽度小于相邻第一电极之间的距离，并且小于半导体器件的设计规则的最小值。

公开(公告)号：US20050170608A1

公开(公告)日：2005-08-04

申请号：US10989319

申请日：2004-11-17

申请人： Masahiro Kiyotoshi ,  Atsuko Kawasaki ,  Katsuhiko Hieda

发明人： Masahiro Kiyotoshi ,  Atsuko Kawasaki ,  Katsuhiko Hieda

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L21/76235 ,  H01L21/76229 ,  H01L27/10861

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed on the semiconductor substrate; and an isolation region filled in the trench, the isolation region having a lower wet etching rate near the upper edge of said trench than that of the lower portion of said trench, and the wet etching rate of the isolation region being almost uniform on a plane parallel to the surface of the semiconductor substrate.

摘要翻译： 半导体器件包括半导体衬底; 形成在半导体衬底上的沟槽; 以及填充在所述沟槽中的隔离区域，所述隔离区域在所述沟槽的上边缘附近具有比所述沟槽的下部的较低的湿蚀刻速率，并且所述隔离区域的湿蚀刻速率在平面上几乎均匀 平行于半导体衬底的表面。

公开(公告)号：US20050087874A1

公开(公告)日：2005-04-28

申请号：US10997889

申请日：2004-11-29

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L23/48 ,  H01L27/02 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device comprising a bit line extending in a first direction, a plurality of transistors electrically connected to the bit line, a plurality of first electrodes arranged in the first direction and electrically connected to the transistors, a dielectric film covering upper and side surfaces of the first electrodes, and a second electrode covering the dielectric film, wherein a width of the first electrode is smaller than a distance between adjacent first electrodes and smaller than the minimum value of design rule of the semiconductor device.

摘要翻译： 公开了一种半导体器件，包括沿第一方向延伸的位线，电连接到位线的多个晶体管，沿第一方向布置并电连接到晶体管的多个第一电极，覆盖上部和侧部的电介质膜 第一电极的表面和覆盖电介质膜的第二电极，其中第一电极的宽度小于相邻第一电极之间的距离，并且小于半导体器件的设计规则的最小值。

公开(公告)号：US06515338B1

公开(公告)日：2003-02-04

申请号：US09533765

申请日：2000-03-23

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽，将第一绝缘体 在第一凹槽中形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，在第二绝缘膜上形成第二绝缘膜 由虚拟栅极层和第一绝缘膜包围的半导体衬底，去除伪栅极层和第一膜以形成第二沟槽，在第二沟槽中的半导体衬底上形成栅极绝缘膜，并在栅极电极上形成栅电极 栅极绝缘膜在第二凹槽中。

公开(公告)号：US06373085B1

公开(公告)日：2002-04-16

申请号：US09216835

申请日：1998-12-21

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L27108

CPC分类号： H01L29/945 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1087

摘要： A memory cell incorporated in a dynamic RAM is disclosed. The memory cell comprises a capacitor having a storage electrode formed in a trench, a first semiconductor layer formed on the capacitor, a connection member formed in the hole, a second semiconductor layer formed on the first semiconductor layer and the connection member, and a transistor formed in the second semiconductor layer. One of the source and the drain of the transistor is connected to the connection member in a direction of lamination of the substrate and the layers.

摘要翻译： 公开了结合在动态RAM中的存储单元。 存储单元包括具有形成在沟槽中的存储电极的电容器，形成在电容器上的第一半导体层，形成在孔中的连接构件，形成在第一半导体层上的第二半导体层和连接构件，以及晶体管 形成在第二半导体层中。 晶体管的源极和漏极之一沿着衬底和层的叠层方向连接到连接构件。

公开(公告)号：US06351006B1

公开(公告)日：2002-02-26

申请号：US09436635

申请日：1999-11-09

申请人： Koji Yamakawa ,  Osamu Arisumi ,  Katsuhiko Hieda ,  Tsunetoshi Arikado ,  Hideyuki Kanai

发明人： Koji Yamakawa ,  Osamu Arisumi ,  Katsuhiko Hieda ,  Tsunetoshi Arikado ,  Hideyuki Kanai

IPC分类号： H01C2994

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/60

摘要： A semiconductor device comprises a semiconductor substrate and a capacitor provided above the semiconductor substrate and having an upper electrode, a lower electrode, and a dielectric film provided between the upper electrode and the lower electrode. At least one of the electrodes comprises an SrRuO3 film provided near the dielectric film and a conductive film made of conductive material other than SrRuO3 and provided far from the dielectric film.

摘要翻译： 半导体器件包括设置在半导体衬底上方的半导体衬底和电容器，并具有设置在上电极和下电极之间的上电极，下电极和电介质膜。 电极中的至少一个包括设置在电介质膜附近的SrRuO 3膜和由SrRuO 3以外的导电材料制成并且远离电介质膜设置的导电膜。

公开(公告)号：US06124189A

公开(公告)日：2000-09-26

申请号：US818079

申请日：1997-03-14

申请人： Toru Watanabe ,  Katsuya Okumura ,  Katsuhiko Hieda

发明人： Toru Watanabe ,  Katsuya Okumura ,  Katsuhiko Hieda

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/768 ,  H01L29/66545

摘要： A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer. Subsequent steps include: removing the first insulating layer, thereby forming an unfilled region above the polysilicon layer; depositing a metal such as tungsten in the unfilled region and the contact hole; and polishing the deposited metal layer to planarize the upper surface of the metal with the upper surface of the second insulating layer.

摘要翻译： 用于形成金属带状多晶硅栅极并用于同时形成带状金属多晶硅栅极和金属接触填充的方法包括以下步骤：在硅衬底的表面上形成栅极电介质层; 在栅介质层上形成多晶硅层; 在所述多晶硅层上形成第一绝缘层; 在所述多晶硅层和所述第一绝缘层的任一侧上形成绝缘间隔物; 以及在所述硅衬底的表面中形成离子注入区。 接下来，在硅衬底上沉积第二绝缘层，并且使用化学机械抛光来抛光第二绝缘层，以使第二绝缘层的上表面与第一绝缘层的上表面平坦化作为抛光停止件。 然后，在第二绝缘膜中形成接触孔，其中接触孔与多晶硅层和第一绝缘层横向隔开。 随后的步骤包括：去除第一绝缘层，从而在多晶硅层上形成未填充区域; 在未填充区域和接触孔中沉积诸如钨的金属; 并且研磨沉积的金属层以使第二绝缘层的上表面平坦化金属的上表面。