公开(公告)号：US06541278B2

公开(公告)日：2003-04-01

申请号：US09492350

申请日：2000-01-27

申请人： Kiyoyuki Morita ,  Takashi Ohtsuka ,  Michihito Ueda

发明人： Kiyoyuki Morita ,  Takashi Ohtsuka ,  Michihito Ueda

IPC分类号： C23C1606

CPC分类号： H01L29/513 ,  C23C16/409 ,  C23C16/4485 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31691 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor substrate is placed within a housing. By supplying organometallic complexes and carbon dioxide in a supercritical state into the housing, a BST thin film is formed on a platinum thin film, while at the same time, carbon compounds, which are produced when the BST thin film is formed are removed. The solubility of carbon compounds in the supercritical carbon dioxide is very high, and yet the viscosity of the supercritical carbon dioxide is low. Accordingly, the carbon compounds are removable efficiently from the BST thin film. An oxide or nitride film may also be formed by performing oxidation or nitriding at a low temperature using water in a supercritical or subcritical state, for example.

摘要翻译： 将半导体衬底放置在壳体内。 通过将超临界状态的有机金属配合物和二氧化碳供给到壳体中，在铂薄膜上形成BST薄膜，同时除去形成BST薄膜时产生的碳化合物。 碳化合物在超临界二氧化碳中的溶解度非常高，而超临界二氧化碳的粘度低。 因此，碳化合物可从BST薄膜有效地去除。 氧化物或氮化物膜也可以通过使用例如超临界或亚临界状态的水在低温下进行氧化或氮化来形成。

公开(公告)号：US20110001193A1

公开(公告)日：2011-01-06

申请号：US12882643

申请日：2010-09-15

申请人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

发明人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

IPC分类号： H01L27/092

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.

摘要翻译： 半导体包括n沟道晶体管形成区域和p沟道晶体管形成区域，它们被元件隔离区域划分。 在n沟道晶体管形成区域中由接触插塞引起的应力和由p沟道晶体管形成区域中的接触插塞引起的应力彼此不同。 由此，能够增加n沟道晶体管和p沟道晶体管的驱动电流，而不改变有源区和元件隔离区的尺寸。

公开(公告)号：US20090200582A1

公开(公告)日：2009-08-13

申请号：US12405668

申请日：2009-03-17

申请人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

发明人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

IPC分类号： H01L29/40

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.

摘要翻译： 半导体包括n沟道晶体管形成区域和p沟道晶体管形成区域，它们被元件隔离区域划分。 在n沟道晶体管形成区域中由接触插塞引起的应力和由p沟道晶体管形成区域中的接触插塞引起的应力彼此不同。 由此，能够增加n沟道晶体管和p沟道晶体管的驱动电流，而不改变有源区和元件隔离区的尺寸。

公开(公告)号：US07493353B2

公开(公告)日：2009-02-17

申请号：US10781819

申请日：2004-02-20

申请人： Michihito Ueda ,  Kiyoyuki Morita

发明人： Michihito Ueda ,  Kiyoyuki Morita

IPC分类号： G06J1/00 ,  G06G7/00

CPC分类号： G06N7/005

摘要： A stochastic processor of the present invention includes a fluctuation generator configured to output an analog quantity having a fluctuation, a fluctuation difference calculation means configured to output fluctuation difference data with an output of the fluctuation generator added to analog difference between two data, a thresholding unit configured to perform thresholding on an output of the fluctuation difference calculation means to thereby generate a pulse, and a pulse detection means configured to detect the pulse output from the thresholding unit.

摘要翻译： 本发明的随机处理器包括：波动发生器，被配置为输出具有波动的模拟量;波动差计算装置，被配置为输出波动差分数据，其中波动发生器的输出相加于两个数据之间的模拟差值;阈值单元 被配置为对所述波动差计算装置的输出执行阈值处理，从而生成脉冲;以及脉冲检测装置，被配置为检测从所述阈值单元输出的脉冲。

公开(公告)号：US20060076558A1

公开(公告)日：2006-04-13

申请号：US11217394

申请日：2005-09-02

申请人： Kiyoyuki Morita ,  Hiroyuki Kamada ,  Keita Uchiyama

发明人： Kiyoyuki Morita ,  Hiroyuki Kamada ,  Keita Uchiyama

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the present invention is to prevent a junction leakage current generation across a pn junction formed under a silicide layer, even when a direct probing to an electrode formed of the silicide layer is performed. There is provided a semiconductor device including an element for evaluation, wherein the element for evaluation includes a device isolation region, a first diffusion layer region formed adjacent to the device isolation region, an electrode for probe formed to be electrically connected to the first diffusion layer region, a semiconductor region which is formed so as to contact to the first diffusion layer region, and has a conductivity type different from that of the first diffusion layer region, and an evaluation pattern which is formed to be electrically connected to the electrode for probe, and includes at least a part of the first diffusion layer region, and wherein a second diffusion layer region which has the same conductivity type as that of the first diffusion layer region is selectively formed under the first diffusion layer region formed under the electrode for probe to be contacted to the first diffusion layer region and the semiconductor region.

摘要翻译： 本发明的目的是为了防止在形成于硅化物层下面的pn结两端产生结漏电流，即使直接探测由硅化物层形成的电极。 提供了一种包括用于评估的元件的半导体器件，其中用于评估的元件包括器件隔离区域，与器件隔离区域相邻形成的第一扩散层区域，形成为与第一扩散层电连接的探针用电极 区域，形成为与第一扩散层区域接触的半导体区域，并且具有与第一扩散层区域不同的导电型，以及形成为电连接到探针用电极的评价图案 并且包括第一扩散层区域的至少一部分，并且其中具有与第一扩散层区域相同的导电类型的第二扩散层区域选择性地形成在形成在探针电极下方的第一扩散层区域的下方 以与第一扩散层区域和半导体区域接触。

公开(公告)号：US20050093043A1

公开(公告)日：2005-05-05

申请号：US10980309

申请日：2004-11-04

申请人： Kiyoyuki Morita ,  Noboru Yamada ,  Akihito Miyamoto ,  Takashi Ohtsuka ,  Hideyuki Tanaka

发明人： Kiyoyuki Morita ,  Noboru Yamada ,  Akihito Miyamoto ,  Takashi Ohtsuka ,  Hideyuki Tanaka

IPC分类号： G11C16/02 ,  H01L27/11 ,  H01L27/24 ,  H01L45/00 ,  H01L29/76 ,  H01L21/48

CPC分类号： G11C13/0004 ,  G11C14/009 ,  H01L27/1104 ,  H01L27/24 ,  H01L45/04 ,  H01L45/145

摘要： A non-volatile memory comprising: a first substrate (100) and a second substrate (110), the first substrate (100) having a plurality of switching elements (4) arranged in matrix, and a plurality of first electrodes (18) connected to the switching element (4), the second substrate (110) having a conductive film (32), and a recording layer (34) whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes (18) are integrally covered by the recording layer (34), the recording layer (34) thereby being held between the plurality of first electrodes (18) and the conductive film (32); the first substrate (100) further comprising a second electrode (22), the second electrode (22) being electrically connected to the conductive film (32), the voltage of which is maintained at a set level while applying current to the recording layer (34). This non-volatile memory achieves high integration at low cost.

摘要翻译： 一种非易失性存储器，包括：第一基板（100）和第二基板（110），所述第一基板（100）具有布置成矩阵的多个开关元件（4），并且多个第一电极（18）被连接 至所述开关元件（4），所述第二基板（110）具有导电膜（32）以及其电阻值通过施加电脉冲而改变的记录层（34），其中所述多个第一电极（18）为 由记录层（34）整体覆盖，记录层（34）由此保持在多个第一电极（18）和导电膜（32）之间; 所述第一基板（100）还包括第二电极（22），所述第二电极（22）电连接到所述导电膜（32），其电压保持在设定电平，同时向所述记录层施加电流（ 34）。 这种非易失性存储器以低成本实现高集成度。

公开(公告)号：US06859381B2

公开(公告)日：2005-02-22

申请号：US10791781

申请日：2004-03-04

申请人： Takashi Ohtsuka ,  Kiyoyuki Morita ,  Michihito Ueda

发明人： Takashi Ohtsuka ,  Kiyoyuki Morita ,  Michihito Ueda

IPC分类号： G11C11/22 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C16/0408 ,  H01L27/11507 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.

摘要翻译： 具有浮置栅电极的非易失性半导体存储元件，以及与浮置栅电极连接的介质电容器和强电介质电容器。 通过在第一极化电压供给端子和第二极化电压供给端子之间施加电压，在铁电体电容器的铁电体膜中产生作为信息的极化。 另外，当在与源极和漏极区域连接的接地端子和电源电压端子之间施加读出电压时，与保持在电源电压的电荷的状态相对应地，MISFET被接通或断开 浮栅电极，从而读出浮栅电极内的信息。

公开(公告)号：US06847543B2

公开(公告)日：2005-01-25

申请号：US10684419

申请日：2003-10-15

申请人： Kenji Toyoda ,  Kiyoyuki Morita

发明人： Kenji Toyoda ,  Kiyoyuki Morita

IPC分类号： G11C14/00 ,  G11C16/02 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C14/00 ,  G11C14/0063 ,  G11C14/0072 ,  G11C14/0081 ,  G11C14/009

摘要： A non-volatile memory circuit comprising first and second transistors (101, 102) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a first inverter is formed; third and fourth transistors (103, 104) each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a second inverter is formed; a fifth transistor (105) provided with a gate, which is connected to a word line (107), and which is connected between a first bit line (108) and an input terminal of the second inverter; a sixth transistor (106) provided with a gate, which is connected to the word line (107), and which is connected between a second bit line (109) and an input terminal of the first inverter; and first and second resistor elements (114, 115) which are serially connected to the first and second inverters, respectively, wherein the input terminal and an output terminal of the first inverter are connected to an output terminal and the input terminal of the second inverter, respectively, and the resistance values of the first and second resistor elements (114, 115), which are connected to a ground line (111), are electrically variable.

摘要翻译： 一种非易失性存储器电路，包括每个具有栅极和漏极的第一和第二晶体管（101,102），其中这些晶体管的栅极彼此连接，并且这些晶体管的漏极彼此连接，由此第一 逆变器形成; 每个具有栅极和漏极的第三和第四晶体管（103,104），其中这些晶体管的栅极彼此连接，并且这些晶体管的漏极彼此连接，从而形成第二反相器; 具有连接到字线（107）并连接在第一位线（108）和第二反相器的输入端子之间的栅极的第五晶体管（105） 设置有与所述字线（107）连接的栅极的第六晶体管（106），连接在第二位线（109）和第一反相器的输入端子之间; 以及分别与第一和第二反相器串联连接的第一和第二电阻器元件（114,115），其中第一反相器的输入端子和输出端子连接到输出端子，第二反相器的输入端子 并且连接到接地线（111）的第一和第二电阻器元件（114,115）的电阻值是电可变的。

公开(公告)号：US06720596B2

公开(公告)日：2004-04-13

申请号：US09977310

申请日：2001-10-16

申请人： Takashi Ohtsuka ,  Kiyoyuki Morita ,  Michihito Ueda

发明人： Takashi Ohtsuka ,  Kiyoyuki Morita ,  Michihito Ueda

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C16/0408 ,  H01L27/11507 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor storage element, which is provided with a floating gate electrode, and a dielectric capacitor and a ferroelectric capacitor both connected to the floating gate electrode. By applying voltage between a first polarization voltage supplying terminal and a second polarization voltage supplying terminal, polarization serving as information is generated in the ferroelectric film of the ferroelectric capacitor. Additionally, when a read-out voltage is applied between the ground terminal and the power source voltage terminal that are in connection with the source and drain regions, the MISFET is turned either on or off in correspondence to the state of the charge held in the floating gate electrode, and thus information within the floating gate electrode is read out.

摘要翻译： 具有浮置栅电极的非易失性半导体存储元件，以及与浮置栅电极连接的介质电容器和强电介质电容器。 通过在第一极化电压供给端子和第二极化电压供给端子之间施加电压，在铁电体电容器的铁电体膜中产生作为信息的极化。 另外，当在与源极和漏极区域连接的接地端子和电源电压端子之间施加读出电压时，与保持在电源电压的电荷的状态相对应地，MISFET被接通或断开 浮栅电极，从而读出浮栅电极内的信息。

公开(公告)号：US07507297B2

公开(公告)日：2009-03-24

申请号：US10514811

申请日：2003-05-12

申请人： Yousuke Irie ,  Kiyoyuki Morita ,  Masaaki Suzuki ,  Akihisa Adachi ,  Masahiko Hashimoto

发明人： Yousuke Irie ,  Kiyoyuki Morita ,  Masaaki Suzuki ,  Akihisa Adachi ,  Masahiko Hashimoto

IPC分类号： B08B7/04 ,  B08B7/00 ,  B08B5/00 ,  B08B3/00 ,  B08B3/02 ,  B08B3/04

CPC分类号： B08B7/0021 ,  Y10S134/902

摘要： A cleaning effect is improved by cleaning a component that has a recess structure by using a cleaning medium of a liquefied gas or a supercritical fluid. By the cleaning method of removing adhering substances adhering to at least the surface of the recess structure of the component that has the recess structure, cleaning is carried out by using the supercritical gas or the liquefied gas so that the cleaning medium spreads over the surface of the recess structure.

摘要翻译： 通过使用液化气体或超临界流体的清洁介质清洗具有凹陷结构的部件来提高清洁效果。 通过除去附着于至少具有凹部结构的部件的凹部结构的表面的附着物质的清洗方法，通过使用超临界气体或液化气体进行清洗，使得清洗介质在 凹槽结构。