公开(公告)号：US20060023500A1

公开(公告)日：2006-02-02

申请号：US11194111

申请日：2005-07-28

申请人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

发明人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/20 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344

摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

摘要翻译： 当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12） ）。 在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据 外部读取访问请求到非冗余存储器区域。 在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。 随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。 此后，读出重写操作信息（S18）。 因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

公开(公告)号：US06879521B2

公开(公告)日：2005-04-12

申请号：US10369496

申请日：2003-02-21

申请人： Takaaki Furuyama

发明人： Takaaki Furuyama

IPC分类号： G11C16/02 ,  G11C16/30 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/30

摘要： It is intended to provide a nonvolatile semiconductor memory device which maintains the maximum number of over-erase memory cells which are conductive when adjusting the threshold voltage after data erase by controlling the gate voltage of a memory cell continuously in order to adjust the threshold voltage in a short time and a nonvolatile voltage adjustment method. There is formed a feedback loop for controlling the number of memory cells to be conductive in a memory cell group by controlling a gate voltage generating circuit through a differential amplifier from a drain terminal and the gate voltage generating circuit is controlled by the differential amplifier so as to maintain the drain voltage at a predetermined drain voltage VRF. A variable gate voltage can be controlled continuously by a feedback loop for controlling the variable gate voltage based on a difference voltage between the drain voltage and the predetermined drain voltage. Thus, effective threshold voltage adjustment operation is enabled corresponding to a current supply capacity regardless of the current supply capacity of the drain voltage generating circuit.

摘要翻译： 旨在提供一种非易失性半导体存储器件，其通过连续地控制存储单元的栅极电压来调节数据擦除后的阈值电压时，保持导通的最大数目的过擦除存储器单元，以便调整阈值电压 短时间和非挥发性电压调节方法。 通过从漏极端子通过差分放大器控制栅极电压产生电路并且由栅极电压产生电路由差分放大器控制，形成用于控制存储器单元组中导电的存储器单元的数量的反馈回路，以便 以将漏极电压保持在预定的漏极电压VRF。 可以通过反馈环路连续地控制可变栅极电压，用于基于漏极电压和预定漏极电压之间的差电压来控制可变栅极电压。 因此，与漏极电压产生电路的电流供应能力无关，能够对应于电流供应容量启用有效阈值电压调整操作。

公开(公告)号：US06490215B2

公开(公告)日：2002-12-03

申请号：US09861545

申请日：2001-05-22

申请人： Kazufumi Komura ,  Takaaki Furuyama ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

摘要翻译： 一种半导体存储器件，其抑制来自地址信号线的布局的电路面积的增加。 半导体存储器件包括刷新地址计数器，开关电路和地址保持电路。 刷新地址计数器响应于刷新请求信号产生与存储体相关联的刷新地址信号。 开关电路根据刷新请求信号有选择地输出外部地址信号和由刷新地址计数器之一产生的刷新地址信号。 每个地址保持电路保持从开关电路输出的刷新地址信号或外部地址信号，并将保持的地址信号提供给相关的一个存储体。

公开(公告)号：US06310825B1

公开(公告)日：2001-10-30

申请号：US09671647

申请日：2000-09-28

申请人： Takaaki Furuyama

发明人： Takaaki Furuyama

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： A semiconductor memory device includes a control circuit that sets read and write latency periods such that the write data input circuit is activated and acquires the write data after the receipt of a write command and upon the lapse of the write latency period. The write latency period of the memory device is set to be one latency value less than the read latency period.

摘要翻译： 半导体存储器件包括控制电路，该控制电路设置读和写等待时间周期，使得写数据输入电路被激活，并且在接收到写命令之后并且在写等待时间段之后获取写数据。 存储器件的写入等待时间周期被设置为小于读取的等待时间周期的一个等待时间值。

公开(公告)号：US6097658A

公开(公告)日：2000-08-01

申请号：US189148

申请日：1998-11-10

申请人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

发明人： Yasuharu Satoh ,  Yoshihiro Takemae ,  Takaaki Furuyama ,  Mitsuhiro Nagao ,  Masahiro Niimi

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/143

摘要： A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

摘要翻译： 具有多个存储单元的DRAM（动态随机存取存储器）包括数据读/写电路读取或写入存储单元的数据，自刷新电路刷新存储在存储单元中的数据，以及电源单元， 数据读/写电路和自刷新电路的电力，电力在正常操作模式下具有第一电压电平，在自刷新模式下具有第二电压电平，其中第二电压电平低于 第一电压电平。

公开(公告)号：US4989182A

公开(公告)日：1991-01-29

申请号：US254153

申请日：1988-10-06

申请人： Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Meiko Kobayashi ,  Takaaki Furuyama

发明人： Hirohiko Mochizuki ,  Tsuyoshi Ohira ,  Yukinori Kodama ,  Meiko Kobayashi ,  Takaaki Furuyama

IPC分类号： G11C11/407 ,  G11C8/14 ,  G11C8/18 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C8/18 ,  G11C11/408 ,  G11C8/14

摘要： A dynamic random access memory includes a dummy word line which has an electrical characteristic identical to that of an actual word line. The dummy word line is charged up and is then discharged as in case of the actual word line. A latched row address in a row address latch circuit is reset when the potential of the dummy word line becomes equal to a predetermined low potential due to the discharge operation for the dummy word line.

公开(公告)号：US07889573B2

公开(公告)日：2011-02-15

申请号：US12341886

申请日：2008-12-22

申请人： Makoto Niimi ,  Kenji Nagai ,  Takaaki Furuyama

发明人： Makoto Niimi ,  Kenji Nagai ,  Takaaki Furuyama

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G06F1/10 ,  G11C7/109

摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

摘要翻译： 在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。 设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。 这里，分别提供多个锁存电路以对应于多个信号端子。 多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。 从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。 这有助于减少信号的锁存特性的偏移。

公开(公告)号：US07415568B2

公开(公告)日：2008-08-19

申请号：US11194111

申请日：2005-07-28

申请人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

发明人： Shozo Kawabata ,  Takaaki Furuyama ,  Kenta Kato

IPC分类号： G11C16/02

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C7/20 ,  G11C16/20 ,  G11C16/26 ,  G11C16/344

摘要： When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S11), and read operation information is read out by preferentially using a verify sense amplifier 4 or a high-speed read sense amplifier 3 (S12). Upon completion of latching the read operation information (S13: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S14), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S15), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S17). Thereafter, rewrite operation information is read out (S18). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

摘要翻译： 当初始化操作开始时，设定指示无法访问操作的忙碌状态（S11），并通过优先使用校验读出放大器4或高速读出放大器3读出读操作信息（S12） ）。 在完成对读取操作信息的锁存（S13：Y）时，设定了从非冗余存储器区域通知读取操作的就绪状态（S14），并且根据 外部读取访问请求到非冗余存储器区域。 在非冗余存储器区域中的引导程序等可以与操作信息的读取并行地读出。 随后，读取冗余信息（S17），读出冗余信息（S15），并且在完成读取冗余信息时设置宣告来自所有存储区域的读取访问操作的就绪状态。 此后，读出重写操作信息（S18）。 因此，可以减少从初始化操作开始到读取访问操作开始的时间段。

公开(公告)号：US07239548B2

公开(公告)日：2007-07-03

申请号：US11317082

申请日：2005-12-21

申请人： Kenta Kato ,  Takaaki Furuyama

发明人： Kenta Kato ,  Takaaki Furuyama

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C29/1201 ,  G11C5/14 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/5006

摘要： In Step 1, a bias is applied (ON) to all of vertical rows Z1(0) to Z1(2). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z2(0) where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z2(1) and Z2(2). On the sectors in the horizontal rows Z2(1) and Z2(2), a voltage stress is applied and an access operation is performed. In Step 2, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z1(1) where the defective sector exists and a bias is applied (ON) to the other vertical rows Z1(0) and Z1(2). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z2(0) where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z2(1) and Z2(2). As for the two steps, a voltage stress can be applied once to the sectors other than the defective sector.

摘要翻译： 在步骤1中，对所有垂直行Z 1（0）至Z 1（2）施加偏压（ON）。 相对于水平行，不对缺陷扇区存在并且向其他水平行Z 2（1）和Z 2施加偏压（ON）的水平行Z 2（0）施加偏压（OFF） （2）。 在水平行Z 2（1）和Z 2（2）的扇区上施加电压应力并进行存取操作。 在步骤2中，相对于垂直列，不对垂直行Z 1（1）施加偏压，其中存在缺陷扇区并且向其它垂直行Z 1（0）施加偏压（ON） ）和Z 1（2）。 对于水平行，对存在缺陷扇区的水平行Z 2（0）施加偏压（ON），并且不向其他水平行Z 2（1）和Z 2施加偏压（OFF） （2）。 对于两个步骤，可以对除了缺陷扇区之外的扇区施加一次电压应力。

公开(公告)号：US07212443B2

公开(公告)日：2007-05-01

申请号：US11062662

申请日：2005-02-23

申请人： Takaaki Furuyama

发明人： Takaaki Furuyama

IPC分类号： G11C16/04

CPC分类号： G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C2216/10 ,  G11C2216/14 ,  G11C2216/16

摘要： A non-volatile memory in which a plurality of memory cells connected to a same word line are entirely written with data. Source lines SL separated from each other in column units is arranged on each memory cell of a memory cell array. When writing data, one of either a first or a second source voltage is applied to each source line in accordance with data that is to be written. After a first control voltage of negative voltage is applied, a second control voltage of high voltage is applied to the word line with the voltage of each source line SL in a maintained state. Therefore, each memory cell is erased or programmed in accordance with the voltage applied to the respective source line.

摘要翻译： 连接到同一字线的多个存储单元完全用数据写入的非易失性存储器。 在列单元中彼此分离的源极线SL布置在存储器单元阵列的每个存储单元上。 当写入数据时，根据要写入的数据将第一或第二源电压中的一个施加到每个源极线。 在施加负电压的第一控制电压之后，将高电压的第二控制电压施加到字线，并且每个源极线SL的电压处于维持状态。 因此，每个存储单元根据施加到相应源极线的电压被擦除或编程。