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    Non-volatile semiconductor memory device
    31.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08446777B2

    公开(公告)日：2013-05-21

    申请号：US13280618

    申请日：2011-10-25

    申请人： Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

    发明人： Koki Ueno ,  Eietsu Takahashi ,  Shigefumi Irieda ,  Yasuhiro Shiino ,  Manabu Sakaniwa

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/14 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/344

    摘要： A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number

    摘要翻译： 根据本发明的一个实施例的非易失性半导体存储器件包括存储单元阵列和控制单元。 控制单元被配置为控制擦除操作，擦除验证操作和升压操作的重复。 控制单元被配置为执行将存储单元从过擦除状态设置为第一阈值电压分布状态的软编程操作，当在一系列擦除操作中擦除电压应用的数量多于第一阈值电压分配状态时， 数字和小于第二个数字（第一个数字<第二个数字）。 当擦除电压应用的数量等于或小于第一数量或等于或大于第二数量时，控制单元被配置为不执行软编程操作。

    SEMICONDUCTOR STORAGE DEVICE
    32.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20130058171A1

    公开(公告)日：2013-03-07

    申请号：US13425121

    申请日：2012-03-20

    申请人： Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

    发明人： Yasuhiro SHIINO ,  Shigefumi Irieda ,  Kenri Nakai ,  Eietsu Takahashi ,  Koki Ueno

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3418

    摘要： A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.

    摘要翻译： 半导体存储装置具有多个存储单元，每个存储单元具有形成在阱上的控制栅极。 半导体存储装置具有向井和控制门施加电压的控制电路。 在存储单元的擦除操作中，控制电路施加第一擦除电压的第一脉冲波，该第一脉冲波逐步上升到阱，然后向阱施加第二擦除电压的第二脉冲波。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    33.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20130003454A1

    公开(公告)日：2013-01-03

    申请号：US13537317

    申请日：2012-06-29

    申请人： Toshiaki Edahiro ,  Masahiro Noguchi ,  Koki Ueno

    发明人： Toshiaki Edahiro ,  Masahiro Noguchi ,  Koki Ueno

    IPC分类号： G11C16/26 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483

    摘要： A non-volatile semiconductor memory device according to embodiments has a memory cell array and a reading circuit, and, in a reading sequence, the reading circuit executes a prereading operation of supplying a first reading voltage to an adjacent word line and supplying a first reading pass voltage to a selected word line, and after executing the prereading operation, executes a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage to the adjacent word line while sensing a plurality of electrical physical amounts of a target memory cell with different reading conditions.

    摘要翻译： 根据实施例的非易失性半导体存储器件具有存储单元阵列和读取电路，并且在读取序列中，读取电路执行向相邻字线提供第一读取电压并提供第一读数的预读操作 将电压传递到所选择的字线，并且在执行预读操作之后，执行向所选择的字线提供固定的第二读取电压并向固定的第二读取通过电压提供固定的第二读取通过电压的主要读取操作，同时感测多个 具有不同读取条件的目标存储单元的电物理量。

    Non-volatile semiconductor memory device and process of manufacturing the same
    34.
    发明授权
    Non-volatile semiconductor memory device and process of manufacturing the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07948038B2

    公开(公告)日：2011-05-24

    申请号：US12789224

    申请日：2010-05-27

    申请人： Toshitake Yaegashi ,  Koki Ueno

    发明人： Toshitake Yaegashi ,  Koki Ueno

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

    摘要翻译： 在器件隔离沟槽中，第一器件隔离绝缘膜形成为具有凹槽，并且在凹部中形成第二器件隔离绝缘膜。 第一器件隔离绝缘膜的两端的最上部位于比第二器件隔离绝缘膜的两端的最上部更高位置。

    Non-volatile semiconductor memory device and process of manufacturing the same
    35.
    发明授权
    Non-volatile semiconductor memory device and process of manufacturing the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07732873B2

    公开(公告)日：2010-06-08

    申请号：US12367590

    申请日：2009-02-09

    申请人： Toshitake Yaegashi ,  Koki Ueno

    发明人： Toshitake Yaegashi ,  Koki Ueno

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

    摘要翻译： 在器件隔离沟槽中，第一器件隔离绝缘膜形成为具有凹槽，并且在凹部中形成第二器件隔离绝缘膜。 第一器件隔离绝缘膜的两端的最上部位于比第二器件隔离绝缘膜的两端的最上部更高位置。

    Nonvolatile semiconductor memory and driving method thereof
    36.
    发明授权
    Nonvolatile semiconductor memory and driving method thereof 失效
    非易失性半导体存储器及其驱动方法

    公开(公告)号：US07672169B2

    公开(公告)日：2010-03-02

    申请号：US12033453

    申请日：2008-02-19

    申请人： Koki Ueno

    发明人： Koki Ueno

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a plurality of serially connected memory cells arranged on a P-well area within a semiconductor substrate, select gate transistors connected to one end and the other of the serially connected memory cells, a P-well control circuit which controls the P-well area, a plurality of word lines connected to the plurality of memory cells, a row control circuit which controls the plurality of word lines, and an operation control circuit which controls the P-well control circuit and the row control circuit, wherein, when writing to a selected one of the plurality of memory cells, the operation control circuit controls the P-well control circuit to apply a precharge potential to the P-well area and thus precharge channel areas of the plurality of memory cells.

    摘要翻译： 根据本发明的一个方面的非易失性半导体存储器包括布置在半导体衬底内的P阱区上的多个串联连接的存储单元，连接到串联存储单元的一端和另一个的选择栅极晶体管，P 控制P阱区域的多个字线，连接到多个存储单元的多个字线，控制多个字线的行控制电路以及控制P阱控制电路的操作控制电路 以及行控制电路，其中，当向所述多个存储单元中的所选择的一个存储单元进行写入时，所述操作控制电路控制所述P阱控制电路向所述P阱区域施加预充电电位， 多个存储单元。

    Nonvolatile semiconductor memory device
    39.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08811089B2

    公开(公告)日：2014-08-19

    申请号：US13424788

    申请日：2012-03-20

    申请人： Koki Ueno

    发明人： Koki Ueno

    IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C16/16

    CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/349

    摘要： A nonvolatile semiconductor memory device according to the embodiment comprises a memory cell array including plural memory cells operative to store data nonvolatilely in accordance with plural different threshold voltages; and a control unit operative to, in data write to the memory cell, execute write loops having a program operation for changing the threshold voltage of the memory cell and a verify operation for detecting the threshold voltage of the memory cell after the program operation, the control unit, in data write for changing one threshold voltage of the plural threshold voltages, executing the verify operation, when the number of write loops to the memory cell becomes more than a certain defined number, using a condition that can pass the verify operation easier than that when the number of write loops is equal to or less than the certain defined number.

    摘要翻译： 根据实施例的非易失性半导体存储器件包括存储单元阵列，其包括多个存储单元，用于根据多个不同阈值电压非易失存储数据; 以及控制单元，用于在对存储器单元的数据写入中执行具有用于改变存储单元的阈值电压的编程操作的写入循环和用于在编程操作之后检测存储单元的阈值电压的验证操作， 控制单元，在用于改变多个阈值电压的一个阈值电压的数据写入中，执行验证操作，当使用可以通过验证操作的条件更容易地使得到存储器单元的写入次数变得大于特定定义数量时 写循环数等于或小于某个定义的数字时。