公开(公告)号：US20070049028A1

公开(公告)日：2007-03-01

申请号：US11214684

申请日：2005-08-30

申请人： Krupakar Subramanian ,  Mirzafer Abatchev

发明人： Krupakar Subramanian ,  Mirzafer Abatchev

IPC分类号： B44C1/22 ,  B05C1/00 ,  H01L21/302

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  Y10S977/887 ,  Y10S977/888

摘要： A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.

摘要翻译： 用于形成用于纳米压印光刻的模板的方法包括形成提供从模板基底延伸的地形特征的至少一个柱。 在模板基底和柱上方形成至少一个共形图案层和一个共形间隔层，以及通常多个交替图案层和间隔层。 在图案和间隔层之上形成平坦化的填充层，然后例如使用机械抛光部分去除填料，间隔层和图案层以暴露柱。 执行一个或多个蚀刻以去除柱，填料和间隔层的至少一部分，以导致图案层从间隔层突出并提供模板图案。

公开(公告)号：US20060267075A1

公开(公告)日：2006-11-30

申请号：US11138575

申请日：2005-05-26

申请人： Gurtej Sandhu ,  Mirzafer Abatchev

发明人： Gurtej Sandhu ,  Mirzafer Abatchev

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L29/66825

摘要： Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate dielectric layer. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.

公开(公告)号：US20060258162A1

公开(公告)日：2006-11-16

申请号：US11492323

申请日：2006-07-24

申请人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

发明人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US20060105577A1

公开(公告)日：2006-05-18

申请号：US11319402

申请日：2005-12-29

申请人： Kevin Donohoe ,  Mirzafer Abatchev ,  Robert Veltrop

发明人： Kevin Donohoe ,  Mirzafer Abatchev ,  Robert Veltrop

IPC分类号： H01L21/302 ,  H01L29/00

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823475

摘要： A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are adjusted to permit deposition at low aspect ratio and very little or no deposition at high aspect ratio during the deposition cycle and to permit etching of the material deposited on the low aspect ratio area and etching of the material in the high aspect ratio area during the etching cycle.

摘要翻译： 公开了一种用于蚀刻衬底的调制偏压功率蚀刻方法。 该方法交替地从集成电路器件的低方面区域沉积和蚀刻材料，以在从高方面区域蚀刻材料的同时形成静态区域。 调制脉冲周期和重复频率被调节以允许在低纵横比下进行沉积，并且在沉积周期期间在高纵横比下很少或没有沉积，并允许蚀刻沉积在低纵横比区域上的材料和蚀刻材料 在蚀刻循环期间的高纵横比面积。

公开(公告)号：US20060046484A1

公开(公告)日：2006-03-02

申请号：US10934778

申请日：2004-09-02

申请人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

发明人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US09267605B2

公开(公告)日：2016-02-23

申请号：US13290657

申请日：2011-11-07

申请人： Mirzafer Abatchev ,  Camelia Rusu ,  Brian McMillin

发明人： Mirzafer Abatchev ,  Camelia Rusu ,  Brian McMillin

IPC分类号： C23C16/00 ,  F16K3/02 ,  H01L21/3065 ,  H01J37/32

CPC分类号： F16K3/0209 ,  H01J37/32816 ,  H01J37/32834 ,  H01L21/30655 ,  Y10T137/7837

摘要： A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.

摘要翻译： 其中处理半导体衬底的等离子体处理室的压力控制阀组件包括具有入口，出口和在入口和出口之间延伸的导管的壳体，入口适于连接到等离子体处理室的内部 并且所述出口适于连接到真空泵，所述真空泵在处理所述室中的半导体衬底的快速交替阶段期间将所述等离子体处理室维持在期望的压力设定点。 在其中具有第一组平行槽的固定开槽阀板固定在管道中，使得从腔室排出到管道中的气体通过第一组平行槽。 其中具有第二组平行槽的可移动开槽阀板可相对于固定开槽阀板移动，以调节腔室中的压力。

公开(公告)号：US08834728B1

公开(公告)日：2014-09-16

申请号：US13045394

申请日：2011-03-10

申请人： Yufeng Hu ,  Shawn M. Tanner ,  Ut Tran ,  Zhongyan Wang ,  Mirzafer Abatchev

发明人： Yufeng Hu ,  Shawn M. Tanner ,  Ut Tran ,  Zhongyan Wang ,  Mirzafer Abatchev

IPC分类号： B44C1/22 ,  H01B13/00 ,  G11B7/1387 ,  G11B5/48

CPC分类号： G11B5/4866 ,  G11B7/1387

摘要： A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The method includes providing an NFT using an NFT mask. The NFT resides proximate to the ABS and focuses the laser energy onto the media. A portion of the NFT mask is removed, forming a heat sink mask covering part of the NFT. Optical material(s) are deposited, covering the heat sink mask and the NFT. The heat sink mask is removed, providing an aperture in the optical material(s). A heat sink corresponding to the aperture is provided. The heat sink bottom is thermally coupled with the NFT. A write pole for writing to the media and coil(s) for energizing the write pole are provided. The write pole has a bottom surface thermally coupled with the top surface of the heat sink.

摘要翻译： 一种方法提供一种EAMR传感器。 EAMR传感器与激光器耦合并且具有被配置为在使用期间驻留在介质附近的ABS。 该方法包括使用NFT掩码提供NFT。 NFT靠近ABS，并将激光能量聚焦到介质上。 去除NFT掩模的一部分，形成覆盖NFT部分的散热掩模。 沉积光学材料，覆盖散热掩模和NFT。 去除散热掩模，在光学材料中提供孔。 提供对应于孔的散热器。 散热器底部与NFT热耦合。 提供用于写入介质的写入极和用于激励写入极的线圈。 写极具有与散热器的顶表面热耦合的底表面。

公开(公告)号：US08721902B1

公开(公告)日：2014-05-13

申请号：US13046380

申请日：2011-03-11

申请人： Zhongyan Wang ,  Wei Gao ,  Shawn M. Tanner ,  Mirzafer Abatchev ,  Yanfeng Chen ,  Yufeng Hu

发明人： Zhongyan Wang ,  Wei Gao ,  Shawn M. Tanner ,  Mirzafer Abatchev ,  Yanfeng Chen ,  Yufeng Hu

IPC分类号： B44C1/22

CPC分类号： G11B5/314 ,  G11B5/6088 ,  G11B2005/0021

摘要： A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The EAMR transducer includes an NFT for focusing the energy onto the media. A sacrificial layer is deposited on the NFT and a mask having an aperture provided on the sacrificial layer. A portion of the sacrificial layer exposed by the aperture is removed to form a trench above the NFT. A heat sink is then provided. At least part of the heat sink resides in the trench. The heat sink is thermally coupled to the NFT. Optical material(s) are provided around the heat sink. A write pole configured to write to a region of the media is also provided. The write pole is thermally coupled with the top of the heat sink. Coil(s) for energizing the write pole are also provided.

摘要翻译： 一种方法提供一种EAMR传感器。 EAMR传感器与激光器耦合并且具有被配置为在使用期间驻留在介质附近的ABS。 EAMR传感器包括用于将能量聚焦到介质上的NFT。 牺牲层沉积在NFT上，并且具有设置在牺牲层上的孔的掩模。 被孔径暴露的牺牲层的一部分被去除以在NFT上方形成沟槽。 然后提供散热器。 散热片的至少一部分位于沟槽中。 散热器与NFT热耦合。 光学材料设置在散热器的周围。 还提供了被配置为写入介质的区域的写入极。 写柱与散热器的顶部热耦合。 还提供用于激励写入极的线圈。

公开(公告)号：US20130048082A1

公开(公告)日：2013-02-28

申请号：US13215159

申请日：2011-08-22

申请人： Mirzafer Abatchev ,  Bradley Howard ,  Armen Kirakosian

发明人： Mirzafer Abatchev ,  Bradley Howard ,  Armen Kirakosian

IPC分类号： F17D3/00

CPC分类号： G05B19/418 ,  G05B2219/45031 ,  G05B2219/45212 ,  H01J37/32917 ,  H01J37/32963 ,  H01J37/32972 ,  H01J37/32981 ,  H01J37/3299 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32137 ,  Y02P90/02 ,  Y10T137/0318 ,  Y10T137/8158

摘要： A rapid alternating process system and method of operating a rapid alternating process system includes a rapid alternating process chamber, a plurality of process gas sources coupled to the rapid alternating process chamber, wherein each one of the plurality of process gas sources includes a corresponding process gas source flow controller, a bias signal source coupled to the rapid alternating process chamber, a process gas detector coupled to the rapid alternating process chamber, a rapid alternating process chamber controller coupled to the rapid alternating process chamber, the bias signal source, the process gas detector and the plurality of process gas sources, the rapid alternating process chamber controller including logic for initiating a first rapid alternating process phase including: logic for inputting a first process gas into a rapid alternating process chamber, logic for detecting the first process gas in the rapid alternating process chamber, and logic for applying a corresponding first phase bias signal to the rapid alternating process chamber after the first process gas is detected in the rapid alternating process chamber.

摘要翻译： 快速交替过程系统和操作快速交替过程系统的方法包括快速交替处理室，耦合到快速交替处理室的多个处理气体源，其中多个处理气体源中的每一个包括相应的处理气体 源流控制器，耦合到快速交替处理室的偏置信号源，耦合到快速交替处理室的处理气体检测器，耦合到快速交替处理室的快速交替处理室控制器，偏置信号源，处理气体 检测器和多个处理气体源，所述快速交替处理室控制器包括用于启动第一快速交替处理阶段的逻辑，所述逻辑包括：用于将第一处理气体输入快速交替处理室的逻辑，用于检测所述第一处理气体的逻辑 快速交替处理室，以及应用cor的逻辑 在快速交替处理室中检测到第一处理气体之后，向快速交替处理室响应第一相位偏置信号。

公开(公告)号：US07429536B2

公开(公告)日：2008-09-30

申请号：US11134982

申请日：2005-05-23

申请人： Mirzafer Abatchev ,  Gurtej Sandhu

发明人： Mirzafer Abatchev ,  Gurtej Sandhu

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

摘要翻译： 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。