公开(公告)号：US08834728B1

公开(公告)日：2014-09-16

申请号：US13045394

申请日：2011-03-10

申请人： Yufeng Hu ,  Shawn M. Tanner ,  Ut Tran ,  Zhongyan Wang ,  Mirzafer Abatchev

发明人： Yufeng Hu ,  Shawn M. Tanner ,  Ut Tran ,  Zhongyan Wang ,  Mirzafer Abatchev

IPC分类号： B44C1/22 ,  H01B13/00 ,  G11B7/1387 ,  G11B5/48

CPC分类号： G11B5/4866 ,  G11B7/1387

摘要： A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The method includes providing an NFT using an NFT mask. The NFT resides proximate to the ABS and focuses the laser energy onto the media. A portion of the NFT mask is removed, forming a heat sink mask covering part of the NFT. Optical material(s) are deposited, covering the heat sink mask and the NFT. The heat sink mask is removed, providing an aperture in the optical material(s). A heat sink corresponding to the aperture is provided. The heat sink bottom is thermally coupled with the NFT. A write pole for writing to the media and coil(s) for energizing the write pole are provided. The write pole has a bottom surface thermally coupled with the top surface of the heat sink.

摘要翻译： 一种方法提供一种EAMR传感器。 EAMR传感器与激光器耦合并且具有被配置为在使用期间驻留在介质附近的ABS。 该方法包括使用NFT掩码提供NFT。 NFT靠近ABS，并将激光能量聚焦到介质上。 去除NFT掩模的一部分，形成覆盖NFT部分的散热掩模。 沉积光学材料，覆盖散热掩模和NFT。 去除散热掩模，在光学材料中提供孔。 提供对应于孔的散热器。 散热器底部与NFT热耦合。 提供用于写入介质的写入极和用于激励写入极的线圈。 写极具有与散热器的顶表面热耦合的底表面。

公开(公告)号：US08721902B1

公开(公告)日：2014-05-13

申请号：US13046380

申请日：2011-03-11

申请人： Zhongyan Wang ,  Wei Gao ,  Shawn M. Tanner ,  Mirzafer Abatchev ,  Yanfeng Chen ,  Yufeng Hu

发明人： Zhongyan Wang ,  Wei Gao ,  Shawn M. Tanner ,  Mirzafer Abatchev ,  Yanfeng Chen ,  Yufeng Hu

IPC分类号： B44C1/22

CPC分类号： G11B5/314 ,  G11B5/6088 ,  G11B2005/0021

摘要： A method provides an EAMR transducer. The EAMR transducer is coupled with a laser and has an ABS configured to reside in proximity to a media during use. The EAMR transducer includes an NFT for focusing the energy onto the media. A sacrificial layer is deposited on the NFT and a mask having an aperture provided on the sacrificial layer. A portion of the sacrificial layer exposed by the aperture is removed to form a trench above the NFT. A heat sink is then provided. At least part of the heat sink resides in the trench. The heat sink is thermally coupled to the NFT. Optical material(s) are provided around the heat sink. A write pole configured to write to a region of the media is also provided. The write pole is thermally coupled with the top of the heat sink. Coil(s) for energizing the write pole are also provided.

摘要翻译： 一种方法提供一种EAMR传感器。 EAMR传感器与激光器耦合并且具有被配置为在使用期间驻留在介质附近的ABS。 EAMR传感器包括用于将能量聚焦到介质上的NFT。 牺牲层沉积在NFT上，并且具有设置在牺牲层上的孔的掩模。 被孔径暴露的牺牲层的一部分被去除以在NFT上方形成沟槽。 然后提供散热器。 散热片的至少一部分位于沟槽中。 散热器与NFT热耦合。 光学材料设置在散热器的周围。 还提供了被配置为写入介质的区域的写入极。 写柱与散热器的顶部热耦合。 还提供用于激励写入极的线圈。

公开(公告)号：US20090225602A1

公开(公告)日：2009-09-10

申请号：US12465223

申请日：2009-05-13

申请人： Gurtej S. Sandhu ,  Mirzafer Abatchev

发明人： Gurtej S. Sandhu ,  Mirzafer Abatchev

IPC分类号： G11C16/06 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L29/40114 ,  H01L29/66825

摘要： Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric and/or the intergate dielectric. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.

摘要翻译： 具有分离浮动栅极的浮栅存储器单元有助于降低对隧道电介质和/或栅极间电介质中的局部缺陷的敏感性。 这样的存储器单元还允许每个单元存储多于一个位。 各种实施例的方法有助于制造具有小于用于形成栅极叠层的光刻处理能力的浮动栅极段的尺寸。

公开(公告)号：US07473645B2

公开(公告)日：2009-01-06

申请号：US11601362

申请日：2006-11-16

申请人： Mirzafer Abatchev ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  Krupakar M. Subramanian

IPC分类号： H01L21/331

CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/3148

摘要： The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

摘要翻译： 本发明包括蚀刻衬底的方法，在衬底上形成特征的方法，以及将包含硅，碳和氟的层沉积到半导体衬底上的方法。 在一个实施方案中，蚀刻方法包括形成从基板突出的掩模特征。 该特征具有顶部，相对的侧壁和基部。 在该特征上沉积包含SixCyFz的层，其中“x”为0至0.2，“y”为0.3至0.9，“z”为0.1至0.6。 含有SixCyFz的层和特征相对的侧壁的上部被蚀刻有效地横向凹入靠近特征顶部的上部相对于靠近特征基底的相对侧壁的特征的下部。 在对包含SixCyFz的层进行这种蚀刻以及特征侧壁的上部蚀刻之后，使用掩模特征作为掩模蚀刻衬底。

公开(公告)号：US20070212889A1

公开(公告)日：2007-09-13

申请号：US11372825

申请日：2006-03-09

申请人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

发明人： Mirzafer Abatchev ,  Krupakar Subramanian ,  Baosuo Zhou

IPC分类号： H01L21/467

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

摘要翻译： 公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。 在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。 第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

公开(公告)号：US20060263699A1

公开(公告)日：2006-11-23

申请号：US11134982

申请日：2005-05-23

申请人： Mirzafer Abatchev ,  Gurtej Sandhu

发明人： Mirzafer Abatchev ,  Gurtej Sandhu

IPC分类号： G03F7/26 ,  G03F9/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

摘要翻译： 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。

公开(公告)号：US20060262511A1

公开(公告)日：2006-11-23

申请号：US11492513

申请日：2006-07-24

申请人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

发明人： Mirzafer Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William Rericha ,  D. Durcan

IPC分类号： H05K1/11

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US09099402B2

公开(公告)日：2015-08-04

申请号：US13475109

申请日：2012-05-18

申请人： Mirzafer Abatchev ,  Gurtej Sandhu

发明人： Mirzafer Abatchev ,  Gurtej Sandhu

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/311 ,  H01L21/033 ,  H01L27/105

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

摘要翻译： 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。

公开(公告)号：US08207614B2

公开(公告)日：2012-06-26

申请号：US12186018

申请日：2008-08-05

申请人： Mirzafer Abatchev ,  Gurtej Sandhu

发明人： Mirzafer Abatchev ,  Gurtej Sandhu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

摘要翻译： 公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。 可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。

公开(公告)号：US20110294294A1

公开(公告)日：2011-12-01

申请号：US13207627

申请日：2011-08-11

申请人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

发明人： Mirzafer Abatchev ,  David Wells ,  Baosuo Zhou ,  Krupakar M. Subramanian

IPC分类号： H01L21/311 ,  H01L21/306

CPC分类号： H01L21/31051 ,  H01L21/0337 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31144 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49176 ,  Y10T29/4922 ,  Y10T29/49224

摘要： Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

摘要翻译： 可以使用各种图案转移和蚀刻步骤来产生特征。 传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。 公开了使用填充层和保护层的平面化技术。 具有不同高度的集成电路的部分可以被蚀刻到公共平面。