公开(公告)号：US20100041223A1

公开(公告)日：2010-02-18

申请号：US12478509

申请日：2009-06-04

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Jr Jung Lin ,  Yi-Shien Mor ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen

IPC: H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成第一金属层，第一金属层具有第一 在第二有源区中除去第一金属层的一部分，然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层，形成第一 在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠，从第一栅极堆叠和第二栅极堆叠中去除半导体层，以及在第一栅极堆叠中的第一金属层上形成第二金属层 并且在第二栅极堆叠中部分去除的第一金属层上，第二金属层具有第二功函数。

公开(公告)号：US07625791B2

公开(公告)日：2009-12-01

申请号：US11926830

申请日：2007-10-29

Applicant: Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

Inventor： Joshua Tseng ,  Kang-Cheng Lin ,  Ji-Yi Yang ,  Kuo-Tai Huang ,  Ryan Chia-Jen Chen

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity.

Abstract translation: 金属栅极/高k电介质半导体器件提供形成在半导体衬底上的NMOS栅极结构和PMOS栅极结构。 NMOS栅极结构包括用诸如La的掺杂剂杂质处理的高k栅极电介质，并且PMOS栅极结构的高k栅极电介质材料缺乏该掺杂杂质，并且还包括高功率调制层， k栅极电介质。 用于同时形成NMOS和PMOS栅极结构的工艺包括在其上形成高k栅极介电材料和功函数调谐层，然后从NMOS区选择性地去除功函数调谐层，并进行等离子体处理以选择性地掺杂 具有掺杂剂杂质的NMOS区域中的高k栅极电介质材料，而PMOS区域中的高k栅极电介质基本上不含掺杂剂杂质。

公开(公告)号：US07435640B2

公开(公告)日：2008-10-14

申请号：US11164025

申请日：2005-11-08

Applicant: Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

Inventor： Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

IPC: H01L21/8238

CPC classification number: H01L21/28202 ,  H01L21/28088 ,  H01L21/76822 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract translation: 提供一种制造栅极结构的方法。 首先，在基板上形成牺牲氧化物层。 进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。 接下来，除去牺牲氧化物层。 进行再氧化处理以在衬底的表面上产生界面层。 在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。 限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

公开(公告)号：US20080157231A1

公开(公告)日：2008-07-03

申请号：US12046433

申请日：2008-03-11

Applicant: Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

Inventor： Yun-Ren Wang ,  Ying-Wei Yen ,  Shu-Yen Chan ,  Kuo-Tai Huang

IPC: H01L29/94

CPC classification number: H01L21/28202 ,  H01L21/28088 ,  H01L21/76822 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract translation: 提供一种制造栅极结构的方法。 首先，在基板上形成牺牲氧化物层。 进行氮化处理工艺以重新分配牺牲层和衬底中的氮原子，并产生浓度分布，使得氮的浓度逐渐增加，然后在牺牲氧化物层中具有氮的最大浓度朝向衬底减小。 接下来，除去牺牲氧化物层。 进行再氧化处理以在衬底的表面上产生界面层。 在基板上依次形成高K（介电常数）栅介质层，阻挡层和金属层。 限定金属层，势垒层，高K栅极介电层和界面层以形成层叠栅极结构。

公开(公告)号：US06479344B2

公开(公告)日：2002-11-12

申请号：US09542715

申请日：2000-04-04

Applicant: Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC: H01L218242

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L21/3211 ,  H01L27/10852 ,  H01L28/55

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract translation: 制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。 电容器的结构简单，易于执行。 此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。 制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

公开(公告)号：US06455389B1

公开(公告)日：2002-09-24

申请号：US09872261

申请日：2001-06-01

Applicant: Kuo-Tai Huang ,  Chao-Sheng Lin ,  Li-Wei Cheng

Inventor： Kuo-Tai Huang ,  Chao-Sheng Lin ,  Li-Wei Cheng

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656

Abstract: This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. The present invention uses a liner, whose surface is treated, and a spacer, which is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. This prevents by-product ions from moving from the spacer to other regions by using actions in diffusion and drift to affect the voltage stability of the semiconductor device after the current is connected. This defect will further affect qualities of the semiconductor device.

Abstract translation: 本发明涉及防止副产物从间隔物移动的方法。 特别是通过使用偏移衬垫，具有经处理的表面的衬垫和通过使用原子层沉积法或快速热化学气相沉积法形成的间隔物。 本发明使用表面被处理的衬垫和使用原子层沉积法或快速热化学气相沉积法形成的间隔物。 通过使用扩散和漂移中的动作来影响电流连接后的半导体器件的电压稳定性，防止副产物离子从间隔物移动到其它区域。 该缺陷将进一步影响半导体器件的质量。

公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

Applicant: Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

Abstract translation: 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US06221712B1

公开(公告)日：2001-04-24

申请号：US09385805

申请日：1999-08-30

Applicant: Kuo-Tai Huang ,  Michael W C Huang ,  Tri-Rung Yew

Inventor： Kuo-Tai Huang ,  Michael W C Huang ,  Tri-Rung Yew

IPC: B32B1900

CPC classification number: H01L21/28194 ,  C23C16/405 ,  H01L21/28088 ,  H01L21/31604 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Abstract translation: 一种用于制造栅极结构的方法。 该方法包括提供衬底，随后在衬底的表面上形成氮化物区域。 使用钽（Ta）基有机化合物和作为前体的钛（Ti）基有机化合物，进行有机金属化学气相沉积（OMCVD），从而在衬底上形成Ta2-xTixO5电介质层。 然后依次在Ta2-xTixO5电介质层上形成阻挡层，导电层和抗反射（AR）层。 随后，将AR层，导电层，阻挡层和Ta2-xTixO5电介质层定义为在氮化物区域的衬底上形成栅极结构。 在这种情况下，Ta类有机化合物可以包括Ta-醇盐化合物，而Ti基有机化合物可以包括Ti-醇盐化合物或Ti-酰胺化合物。

公开(公告)号：US06207497B1

公开(公告)日：2001-03-27

申请号：US09565782

申请日：2000-05-05

Applicant: Kuo-Tai Huang ,  Juan-Yuan Wu

Inventor： Kuo-Tai Huang ,  Juan-Yuan Wu

IPC: H01L218242

CPC classification number: H01L21/3185 ,  H01L27/10852 ,  H01L28/84

Abstract: The present invention relates to a method for forming excellent conformity due to improved surface sensitivity. A substrate is providing on which a transistor is formed. Moreover, a blanket first dielectric layer is deposited over the substrate. Then, a first photoresist layer is formed over the dielectric layer, wherein the first photoresist layer is defined and etched to form a contact opening. Further, a first conductive layer is formed to fill the contact opening, and performing an etching process to remove the first conductive layer to form a node contact. Consequentially, a second conductive layer is deposited over the first dielectric layer and the node contact. A second photoresist layer is formed over the second conductive layer, wherein the second photoresist layer is defined and etched to form a storage node as an upper electrode of a capacitor. Next, a hemispherical silicon grain (HSG) is formed over and on a sidewall of the second conductive layer. Treating the hemispherical silicon grain (HSG) layer by rapid thermal nitration (RTN). And then a conformal second dielectric layer is deposited over the hemispherical silicon grain (HSG) and the first dielectric layer after rapid thermal nitration (RTN). Finally, a blanket third conductive layer is formed over the substrate to serve as an upper electrode of the capacitor.

Abstract translation: 本发明涉及由于提高表面灵敏度而形成优异的一致性的方法。 提供其上形成晶体管的衬底。 此外，毯子第一介电层沉积在衬底上。 然后，在电介质层上形成第一光致抗蚀剂层，其中限定和蚀刻第一光致抗蚀剂层以形成接触开口。 此外，形成第一导电层以填充接触开口，并且执行蚀刻工艺以去除第一导电层以形成节点接触。 因此，第二导电层沉积在第一介电层和节点接触之上。 在第二导电层上形成第二光致抗蚀剂层，其中限定和蚀刻第二光致抗蚀剂层以形成作为电容器的上电极的存储节点。 接下来，在第二导电层的侧壁上形成半球形硅晶粒（HSG）。 通过快速热硝化（RTN）处理半球形硅晶粒（HSG）层。 然后在快速热硝化（RTN）之后，半球形硅晶粒（HSG）和第一介电层上沉积共形第二介电层。 最后，在衬底上形成覆盖的第三导电层以用作电容器的上电极。

公开(公告)号：US06200844B1

公开(公告)日：2001-03-13

申请号：US09249503

申请日：1999-02-12

Applicant: Kuo-Tai Huang

Inventor： Kuo-Tai Huang

IPC: H01L218234

CPC classification number: H01L28/40 ,  H01L21/3185 ,  H01L27/1085 ,  H01L28/56

Abstract: A method of manufacturing a dielectric film for a capacitor in a DRAM. A native oxide layer is removed using a rapid ramp process at a pressure lower than 10−5 torr. A nitridation is performed to form a dielectric layer on the surface of a storage electrode. A silicon nitride layer is formed on the dielectric layer. The rapid ramp process is started at a temperature of about 450-550° C. The temperature is raised at a rate of about 80-120° C./minute. The rapid ramp process is stopped at about 700-850° C. The nitridation is performed using a source gas, such as ammonia at about 700-850° C. for a relatively long time of about 10-60 minutes. The dielectric layer includes silicon nitride or silicon-oxy-nitride. An oxide layer is further formed on the silicon nitride layer. The oxide layer is formed by, for example, a rapid thermal process. A gas used in the rapid thermal process can be selected from a group including nitrogen monoxide (N2O), oxygen and combinations of nitrogen monoxide (N2O) and oxygen. The dielectric film structure of the capacitor of the invention can be a double-layer structure such as silicon nitride/silicon oxide or a mono-layer structure, such as silicon nitride.

Abstract translation: 制造DRAM中的电容器用电介质膜的方法。 在低于10-5乇的压力下使用快速斜坡过程去除天然氧化物层。 进行氮化以在存储电极的表面上形成电介质层。 在电介质层上形成氮化硅层。 快速斜坡过程在约450-550℃的温度下开始。温度以约80-120℃/分钟的速率升高。 快速斜坡过程在约700-850℃停止。氮化在约700-850℃下使用源气体，例如氨进行约10-60分钟的较长时间。 电介质层包括氮化硅或氮氧化硅。 在氮化硅层上进一步形成氧化物层。 氧化物层通过例如快速热处理形成。 用于快速热处理的气体可以选自包括一氧化氮（N2O），氧气和一氧化氮（N2O）和氧气的组合的组。 本发明的电容器的电介质膜结构可以是诸如氮化硅/氧化硅的双层结构或诸如氮化硅的单层结构。