公开(公告)号：US20110103154A1

公开(公告)日：2011-05-05

申请号：US12917634

申请日：2010-11-02

申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

IPC分类号： G11C16/12 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

公开(公告)号：US20100032737A1

公开(公告)日：2010-02-11

申请号：US11604679

申请日：2006-11-28

申请人： Kwang Soo Seol ,  Jae Young Choi ,  Dong Kee Yi ,  Seong Jae Choi

发明人： Kwang Soo Seol ,  Jae Young Choi ,  Dong Kee Yi ,  Seong Jae Choi

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/14 ,  G11C11/54 ,  H01L27/228

摘要： A nano-magnetic memory device capable of writing/reading multi data in the nano-magnetic memory cell by controlling an amount of an induced current which is formed after a magnetic nanodot is perturbed and rearranged according to a word line current flowing from the first electrode through a nanowire of the nano-magnetic memory device to the second electrode. Consequently, a size of the memory device is reduced and a density of the memory device may be improved by providing a simplified nano-magnetic memory device of which a cell size is smaller.

摘要翻译： 一种能够通过控制根据从第一电极流过的字线电流对磁性纳米点进行扰动和重新布置之后形成的感应电流的量来在纳米磁性存储单元中写入/读取多个数据的纳米磁性存储器件 通过纳米线的纳米磁性存储器件到第二电极。 因此，存储器件的尺寸减小，并且可以通过提供其单元尺寸较小的简化的纳米磁性存储器件来提高存储器件的密度。

公开(公告)号：US08754466B2

公开(公告)日：2014-06-17

申请号：US13652998

申请日：2012-10-16

申请人： Janggn Yun ,  Kwang Soo Seol ,  Jungdal Choi

发明人： Janggn Yun ,  Kwang Soo Seol ,  Jungdal Choi

IPC分类号： H01L29/792

CPC分类号： H01L29/7827 ,  H01L27/1157 ,  H01L27/11582

摘要： Three-dimensional (3D) semiconductor memory devices are provided. According to the 3D semiconductor memory device, a gate structure includes gate patterns and insulating patterns alternately stacked on a semiconductor substrate. A vertical active pattern penetrates the gate structure. A gate dielectric layer is disposed between a sidewall of the vertical active pattern and each of the gate patterns. A semiconductor pattern is disposed on the gate structure and is connected to the vertical active pattern. A string drain region is formed in a portion of the semiconductor pattern and is spaced apart from the vertical active pattern.

摘要翻译： 提供三维（3D）半导体存储器件。 根据3D半导体存储器件，栅极结构包括交替层叠在半导体衬底上的栅极图案和绝缘图案。 垂直有源图案穿过栅极结构。 栅介质层设置在垂直有源图案的侧壁和每个栅极图案之间。 半导体图案设置在栅极结构上并连接到垂直有源图案。 串联漏极区域形成在半导体图案的一部分中并且与垂直有源图案间隔开。

公开(公告)号：US20130092994A1

公开(公告)日：2013-04-18

申请号：US13585963

申请日：2012-08-15

申请人： Sunil SHIM ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

发明人： Sunil SHIM ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

IPC分类号： H01L29/78

CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

公开(公告)号：US20110312174A1

公开(公告)日：2011-12-22

申请号：US13165256

申请日：2011-06-21

申请人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

发明人： Jaegoo Lee ,  Byungkwan You ,  Youngwoo Park ,  Kwang Soo Seol

IPC分类号： H01L21/3205 ,  H01L21/31

CPC分类号： H01L21/3205 ,  H01L27/11578 ,  H01L27/11582

摘要： Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer.

摘要翻译： 制造三维半导体器件的方法，其可以包括在形成在第一堆叠结构中的第一开口内的侧壁上形成第一间隔物，在间隔物上形成牺牲填充图案以填充第一开口，形成第二堆叠结构， 在所述第一堆叠结构上暴露所述牺牲填充图案的第二开口，在所述第二开口内的侧壁上形成第二间隔件，去除所述牺牲填充图案并移除所述第一间隔件和所述第二间隔件。

公开(公告)号：US20110233648A1

公开(公告)日：2011-09-29

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

摘要翻译： 三维半导体存储器件及其制造方法。 三维半导体器件包括具有布置在衬底上的顺序层叠电极的电极结构，穿透电极结构的半导体图案，以及插入在半导体图案和电极结构之间的包括第一图案和第二图案的存储元件，第一 垂直延伸以横过电极的图案和第二图案水平延伸以跨越半导体图案。

公开(公告)号：US20110090744A1

公开(公告)日：2011-04-21

申请号：US12795196

申请日：2010-06-07

申请人： ByungKyu CHO ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

发明人： ByungKyu CHO ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/3418

摘要： A channel pre-charge method of a nonvolatile memory device including a cell string includes pre-charging a channel of the cell string according to a first word line bias condition and pre-charging the channel of the cell string according to a second word line bias condition, different than the first word line bias condition.

摘要翻译： 包括单元串的非易失性存储器件的通道预充电方法包括根据第一字线偏置条件对单元串的通道进行预充电，并根据第二字线偏置对单元串的通道进行预充电 条件，不同于第一个字线偏差条件。

公开(公告)号：US07662732B2

公开(公告)日：2010-02-16

申请号：US11615360

申请日：2006-12-22

申请人： Seong Jae Choi ,  Kwang Soo Seol ,  Jae Young Choi ,  Dong Kee Yi ,  Seon Mi Yoon

发明人： Seong Jae Choi ,  Kwang Soo Seol ,  Jae Young Choi ,  Dong Kee Yi ,  Seon Mi Yoon

IPC分类号： H01J19/06

CPC分类号： D01F9/12 ,  B82Y10/00 ,  B82Y30/00 ,  H01J29/481 ,  H01J2201/30469 ,  H01J2329/00 ,  Y10S977/742

摘要： A method of preparing a patterned carbon nanotube array a patterned carbon nanotube array prepared thereby are provided. The method includes forming carbon nanotubes in channels of porous templates, arranging the templates in a predetermined pattern on a substrate and selectively removing the templates to expose the carbon nanotubes.

摘要翻译： 提供了一种由其制备的图案化碳纳米管阵列的图案化碳纳米管阵列的制备方法。 该方法包括在多孔模板的通道中形成碳纳米管，将模板以预定图案排列在基板上，并选择性地去除模板以暴露碳纳米管。

公开(公告)号：US20100027351A1

公开(公告)日：2010-02-04

申请号：US12382035

申请日：2009-03-06

申请人： Kwang Soo Seol

发明人： Kwang Soo Seol

IPC分类号： G11C16/04 ,  G06F12/00 ,  G06F12/02

CPC分类号： G11C16/10 ,  G11C11/5628

摘要： A memory device and a memory programming method are provided. The memory device may program data in a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. The memory device may include a memory cell array, a programming unit and a program level stabilization unit. The memory cell array may include a plurality of multi-level cells. The programming unit may be configured to program a first data page in the plurality of multi-level cells and to program a second data page in the plurality of multi-level cells having the programmed first data page. The program level stabilization unit may be configured to stabilize a program level of at least one of the first data page and the second data page.

摘要翻译： 提供了存储器件和存储器编程方法。 存储器件可以在多级单元（MLC）或多位单元（MBC）存储器件中编程数据。 存储器件可以包括存储单元阵列，编程单元和程序级稳定单元。 存储单元阵列可以包括多个多电平单元。 编程单元可以被配置为对多个多电平单元中的第一数据页进行编程，并对具有编程的第一数据页的多个多电平单元编程第二数据页。 程序级稳定单元可以被配置为稳定第一数据页和第二数据页中的至少一个的程序级。

公开(公告)号：US20090292973A1

公开(公告)日：2009-11-26

申请号：US12453814

申请日：2009-05-22

申请人： Kwang Soo Seol ,  Sung Il Park ,  Kyoung Lae Cho ,  In Sung Joe

发明人： Kwang Soo Seol ,  Sung Il Park ,  Kyoung Lae Cho ,  In Sung Joe

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/611 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/27 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/3715 ,  H03M13/47

摘要： Memory devices and/or methods of storing memory data bits may be provided. A memory device may include a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it may be possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

摘要翻译： 可以提供存储器件和/或存储存储器数据位的方法。 存储器装置可以包括包括多个MLC的多级单元（MLC）阵列，错误校正单元，被配置为对要记录在MLC中的数据进行编码，其中编码数据被转换以将编码数据转换为码字， 错误模式分析单元，被配置为分析与码字中包含的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将所分析的第一数据模式转换为第二数据模式。 根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。