-
公开(公告)号:US07645638B2
公开(公告)日:2010-01-12
申请号:US11462568
申请日:2006-08-04
申请人: Young Cheol Kim , Koo Hong Lee , Jae Hak Yee
发明人: Young Cheol Kim , Koo Hong Lee , Jae Hak Yee
CPC分类号: H01L23/49575 , H01L23/3107 , H01L23/3135 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L25/105 , H01L2224/32245 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2225/06562 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle; stacking a second integrated circuit die over the first integrated circuit die in a active side to active side configuration; connecting the first integrated circuit die and the base; connecting the second integrated circuit die and the base; and molding the first integrated circuit die, the second integrated circuit die, the paddle, and the external interconnect with the external interconnect partially exposed.
摘要翻译: 提供了一种可堆叠的多芯片封装系统,包括形成具有基座和尖端的外部互连件和桨叶; 将第一集成电路管芯安装在所述桨上; 将第二集成电路管芯在有源侧的第一集成电路管芯上堆叠到主动侧构造; 连接第一集成电路管芯和基座; 连接第二集成电路管芯和基座; 并且第一集成电路管芯,第二集成电路管芯,焊盘和外部互连件与外部互连部分地露出成型。
-
公开(公告)号:US20090045507A1
公开(公告)日:2009-02-19
申请号:US11435305
申请日:2006-05-15
申请人: Rajendra D. Pendse , Marcos Karnezos , Kyung-Moon Kim , Koo Hong Lee , Moon Hee Lee , Orion Starr
发明人: Rajendra D. Pendse , Marcos Karnezos , Kyung-Moon Kim , Koo Hong Lee , Moon Hee Lee , Orion Starr
CPC分类号: H01L21/563 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/81 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13111 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75252 , H01L2224/81191 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/83907 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要: Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention.
摘要翻译: 用于形成倒装芯片互连的方法,其中凸块互连至少部分地由底部填充限定。 底部填充物包括热固化的材料; 也就是说,提高底部填充材料的温度可导致底部填充物逐步固化,包括凝胶阶段和完全固化的阶段。 根据本发明,在该工艺的至少早期阶段,半导体芯片由用于以特定方式控制组件的温度的热电极承载。 此外,根据本发明的方法制造的倒装芯片互连和倒装芯片封装。
-
公开(公告)号:US20070194463A1
公开(公告)日:2007-08-23
申请号:US11677487
申请日:2007-02-21
申请人: Young Cheol Kim , Koo Hong Lee , Jae Hak Yee
发明人: Young Cheol Kim , Koo Hong Lee , Jae Hak Yee
IPC分类号: H01L23/28
CPC分类号: H01L23/3107 , H01L21/6835 , H01L23/49548 , H01L23/49575 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/05554 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48471 , H01L2224/48472 , H01L2224/73215 , H01L2224/73265 , H01L2224/85001 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06562 , H01L2225/06582 , H01L2225/1029 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/19107 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first L-shaped leadfingers adjacent the single edge, connecting the die pads and the first L-shaped leadfingers, and encapsulating the die pads and portions of the first L-shaped leadfingers to form a first package.
摘要翻译: 集成电路封装系统包括具有与第一集成电路管芯的单个边缘相邻的管芯焊盘的第一集成电路管芯,与单个边缘相邻形成第一L形引线管,连接管芯焊盘和第一L形引线管,以及 封装所述管芯焊盘和所述第一L形引线管的部分以形成第一封装。
-
公开(公告)号:US20070194462A1
公开(公告)日:2007-08-23
申请号:US11677477
申请日:2007-02-21
申请人: Young Cheol Kim , Koo Hong Lee
发明人: Young Cheol Kim , Koo Hong Lee
IPC分类号: H01L23/28
CPC分类号: H01L23/3107 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/4917 , H01L2224/49171 , H01L2224/4943 , H01L2224/73265 , H01L2225/0651 , H01L2225/06562 , H01L2225/06582 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要: An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first bonding lands adjacent the single edge, connecting the die pads and the first bonding lands, and encapsulating the die pads and a portion of the first bonding lands to form a first package.
摘要翻译: 集成电路封装系统包括第一集成电路管芯,其具有仅与第一集成电路管芯的单个边缘相邻的管芯焊盘,形成与单个边缘相邻的第一焊接区域,连接管芯焊盘和第一焊接区域,以及封装管芯焊盘 并且所述第一结合区域的一部分形成第一包装。
-
公开(公告)号:US20060103010A1
公开(公告)日:2006-05-18
申请号:US11164132
申请日:2005-11-10
申请人: Gwang Kim , Koo Hong Lee
发明人: Gwang Kim , Koo Hong Lee
IPC分类号: H01L23/34
CPC分类号: H01L23/36 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package system is provided including: providing a substrate having substrate wiring and a cavity provided therein with a heat sink foil closing off the cavity; attaching a semiconductor die in the cavity to the heat sink foil; and bonding the semiconductor die to the substrate wiring.
摘要翻译: 提供一种半导体封装系统,包括:提供具有衬底布线的衬底和其中设置有封闭空腔的散热片的空腔; 将所述腔中的半导体管芯附接到所述散热片; 以及将所述半导体管芯接合到所述衬底布线。
-
-
-
-