公开(公告)号：US5546054A

公开(公告)日：1996-08-13

申请号：US377524

申请日：1995-01-20

申请人： Marco Maccarrone ,  Marco Olivo ,  Carla M. Golla

发明人： Marco Maccarrone ,  Marco Olivo ,  Carla M. Golla

IPC分类号： G11C17/00 ,  G05F3/24 ,  G05F3/26 ,  H03F1/30 ,  H03B5/24 ,  G05F3/16 ,  H03K3/011 ,  H03K3/03

CPC分类号： G05F3/262

摘要： A current source including a current mirror circuit and an active load circuit which form a reference branch, for setting a reference current value, and a mirroring branch, defining an output current value, connected between supply and ground. A voltage stabilizing transistor is interposed between the current mirror circuit and the load circuit in the reference branch only, and is so biased as to maintain its gate terminal at a predetermined voltage. As such, the potential with respect to ground of the drain terminal of the reference branch load transistor is fixed, so that its drain-source voltage drop (and the current through it) is substantially independent of supply voltage. The current source may be used to advantage in an oscillator for generating the: clock signal of a nonvolatile memory.

摘要翻译： 电流源包括形成用于设定参考电流值的参考支路的电流镜电路和有源负载电路以及连接在电源和地之间的限定输出电流值的镜像支路。 稳压晶体管仅插入在电流镜电路和参考支路中的负载电路之间，并被偏置以将其栅极端子保持在预定电压。 因此，参考分支负载晶体管的漏极端子的接地电位是固定的，使得其漏 - 源电压降（和通过它的电流）基本上不依赖于电源电压。 在振荡器中可以使用电流源来产生非易失性存储器的：时钟信号。

公开(公告)号：US5748548A

公开(公告)日：1998-05-05

申请号：US711132

申请日：1996-09-09

申请人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

发明人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC分类号： G11C5/143 ,  G11C16/30 ,  G11C5/147

摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

公开(公告)号：US5617356A

公开(公告)日：1997-04-01

申请号：US395361

申请日：1995-02-21

申请人： Carla Golla ,  Silvia Padoan ,  Marco Olivo

发明人： Carla Golla ,  Silvia Padoan ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/14 ,  G11C16/16 ,  G11C16/02

CPC分类号： G11C16/16 ,  G11C16/14

摘要： A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.

摘要翻译： 一种用于对电可编程存储器件中的非易失性存储单元进行放电的调节电路，该电路包括连接在编程电压基准和由形成所述存储单元的晶体管的源极端子共享的线之间的至少一个开关， 所述公共线与源极端子之间的至少一个放电连接和接地电压基准，还包括与电流发生器连接的线路的第二连接点和常开开关。 还提供了连接到线路的逻辑电路，用于将存在于其上的电压值与预定值进行比较，并输出用于使开关产生的控制信号。 该解决方案允许在擦除阶段结束时实现线路的缓慢放电阶段。

公开(公告)号：US5600600A

公开(公告)日：1997-02-04

申请号：US381530

申请日：1995-01-31

申请人： Marco Olivo ,  Marco Maccarrone

发明人： Marco Olivo ,  Marco Maccarrone

IPC分类号： G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C29/14

摘要： A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signals to program the cell matrix, and verifying programming correctness.

摘要翻译： 一种用于测试包括单元矩阵的电可编程非易失性存储器和控制存储器编程阶段的连续和定时的内部状态机的方法包括：排除内部状态机，修改至少一个控制信号以编程单元 矩阵和验证编程正确性。

公开(公告)号：US5583820A

公开(公告)日：1996-12-10

申请号：US366211

申请日：1994-12-29

申请人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

发明人： Silvia Padoan ,  Marco Olivo ,  Carla Golla

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C11/407

CPC分类号： G11C5/143 ,  G11C16/30 ,  G11C5/147

摘要： A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

摘要翻译： 一种电路，用于检测在提供给集成到半导体中的存储装置的电源电压中的阈值以下。 比较器耦合在电源线和信号地之间，并具有第一或参考输入和第二或测试信号输入。 稳定电压基准的发生器具有耦合到第一输入的输出和耦合到比较器的第二输入的电源电压的分压器。 电路装置被布置成以较高的电源电压和还提供给存储装置的编程电压来馈送电源。

公开(公告)号：US5581509A

公开(公告)日：1996-12-03

申请号：US356740

申请日：1994-12-15

申请人： Carla M. Golla ,  Marco Olivo

发明人： Carla M. Golla ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C16/08 ,  G11C29/82 ,  G11C8/12

摘要： A double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy comprises a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix; each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated; a first circuit block of said plurality of circuit blocks has the respective carry-in input connected to a reference voltage; each of said circuit blocks is also supplied with a control signal, which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the respective selection signal if the carry-out signal supplying the respective carry-in input is activated, so that two adjacent rows can be simultaneously selected.

摘要翻译： 用于具有冗余的电可擦除和可编程非易失性存储器件的双行地址解码和选择电路包括提供有地址信号的多个相同的电路块，并且每个电路块产生相应的选择信号，该选择信号由特定逻辑配置 所述地址信号用于选择矩阵的特定行; 所述电路块中的每一个还产生提供给后续电路块的进位输入的进位信号，并且当各个选择信号被激活时被激活; 所述多个电路块的第一电路块具有连接到参考电压的相应输入输入; 每个所述电路块还被提供有控制信号，该控制信号由存储器件的控制电路激活，当在存储器件的电擦除之前的预编程操作期间寻址有缺陷的行时，以使得能够激活 如果提供相应进位输入的进位信号被激活，则相应的选择信号被激活，使得可以同时选择两个相邻的行。