公开(公告)号：US20240170046A1

公开(公告)日：2024-05-23

申请号：US17988760

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C11/408 ,  G11C11/4074

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4087

Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.

公开(公告)号：US11968833B2

公开(公告)日：2024-04-23

申请号：US17149782

申请日：2021-01-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H10B43/27 ,  H01L29/10 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/1037 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

公开(公告)号：US11934480B2

公开(公告)日：2024-03-19

申请号：US16508189

申请日：2019-07-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Hung-Sheng Chang ,  Yi-Ching Liu

IPC: G06F17/00 ,  G06F17/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F17/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.

公开(公告)号：US20230317167A1

公开(公告)日：2023-10-05

申请号：US17710683

申请日：2022-03-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng Hao Yeh ,  Wu-Chin Peng ,  Chih-Ming Lin ,  Hang-Ting Lue

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/30 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device and a word line driver thereof are provided. The word line driver includes a first word line signal generator, a second word line signal generator, a first voltage generator, and a second voltage generator. The first word line signal generator selects one of a first voltage and a second voltage to generate a first word line signal according a control signal. The second word line signal generator selects one of a third voltage and a fourth voltage to generate a second word line signal according the control signal. The first voltage generator provides the second voltage, and the second voltage generator provides the fourth voltage, where the first voltage generator is independent to the second voltage generator.

公开(公告)号：US11765901B2

公开(公告)日：2023-09-19

申请号：US17488128

申请日：2021-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/10 ,  H10B43/27 ,  G11C16/26 ,  G11C16/16 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B41/27

Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.

公开(公告)号：US11742025B2

公开(公告)日：2023-08-29

申请号：US17321670

申请日：2021-05-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/08 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array including a plurality of memory cells; a first local signal line decoder coupled to the memory array; a second local signal line decoder coupled to the memory array; and a controller coupled to and controlling the memory array, the first local signal line decoder and the second local signal line decoder, wherein in programming, a threshold voltage distribution of the memory cells is lower than a read voltage; and in erase, the threshold voltage distribution of the memory cells is higher than the read voltage.

公开(公告)号：US20230215502A1

公开(公告)日：2023-07-06

申请号：US17569424

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

公开(公告)号：US20230085583A1

公开(公告)日：2023-03-16

申请号：US17477229

申请日：2021-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three dimension memory device, such as a three dimensional AND flash memory is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches, and a plurality of source line switches. The memory array has a plurality of memory cell rows respectively coupled to a plurality of source lines and bit lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and second transistors. The first transistors are coupled to a common bit line and the bit line. The second transistors are coupled to a common source line and the source lines. The first transistors are P-type transistors or an N-type transistors with a triple-well substrate, and the second transistors are P-type transistor or an N-type transistors with a triple-well substrate.

公开(公告)号：US11495298B1

公开(公告)日：2022-11-08

申请号：US17465651

申请日：2021-09-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Kai Hsu ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/10 ,  G11C15/04 ,  G11C16/28 ,  G11C16/30 ,  G11C16/24

Abstract: A three dimension memory device and a ternary content addressable memory cell are provided. The ternary content addressable memory cell includes a first memory cell, a second memory cell, a first search switch, and a second search switch. The first memory cell is disposed in a first AND type flash memory line. The second memory cell is disposed in a second AND type flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND type flash memory line and a match line, and is controlled by a first search signal to be turned on or cut off. The second search switch is coupled between a second bit line corresponding to the second AND type flash memory line and the match line, and is controlled by a second search signal to be turned on or cut off.

公开(公告)号：US11374018B2

公开(公告)日：2022-06-28

申请号：US16931598

申请日：2020-07-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11529

Abstract: A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor.