公开(公告)号：US09829914B2

公开(公告)日：2017-11-28

申请号：US15424891

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0994 ,  H03L2207/50

Abstract: A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.

公开(公告)号：US09812187B2

公开(公告)日：2017-11-07

申请号：US15424882

申请日：2017-02-05

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

公开(公告)号：US09608624B2

公开(公告)日：2017-03-28

申请号：US14549552

申请日：2014-11-21

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen

IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0948

CPC classification number: H03K17/687 ,  H03K19/018521 ,  H03K19/0948

Abstract: An apparatus for performing signal driving with aid of MOSFET and an associated IC are provided, where the apparatus includes a PMOSFET coupled between a predetermined voltage level and a terminal, and further includes an NMOSFET coupled between the predetermined voltage level and the terminal. The PMOSFET is arranged for selectively driving a signal that passes through the terminal. In addition, the NMOSFET is arranged for selectively driving the signal. Additionally, the apparatus further includes another NMOSFET coupled between another predetermined voltage level and the terminal, wherein the other NMOSFET is arranged for selectively driving the signal. More particularly, the PMOSFET, the NMOSFET, and the other NMOSFET does not drive the signal at the same time. For example, each of the PMOSFET, the NMOSFET, and the other NMOSFET selectively drives the signal to have one of a plurality of logical states.

公开(公告)号：US20170040995A1

公开(公告)日：2017-02-09

申请号：US15183804

申请日：2016-06-16

Applicant: MEDIATEK INC.

Inventor： An-Siou Li ,  Shang-Pin Chen

IPC: H03K17/687

CPC classification number: H03K17/687 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1069 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

Abstract: An apparatus for performing signal driving in an electronic device may include a decoupling capacitor and at least one switching unit (e.g. one or more switching units). The decoupling capacitor may have a first terminal and a second terminal, and may be positioned in an output stage within the electronic device and coupled between a first predetermined voltage level and another predetermined voltage level, where the apparatus may perform signal driving with aid of the output stage. In addition, the aforementioned at least one switching unit may be coupled between one terminal of the first and the second terminals of the decoupling capacitor and at least one of the first predetermined voltage level and the other predetermined voltage level, and may be arranged for selectively disabling the decoupling capacitor.

Abstract translation: 用于在电子设备中执行信号驱动的设备可以包括去耦电容器和至少一个开关单元（例如一个或多个开关单元）。 去耦电容器可以具有第一端子和第二端子，并且可以位于电子设备内的输出级中并且耦合在第一预定电压电平和另一预定电压电平之间，其中该装置可以借助于 输出阶段。 此外，上述至少一个开关单元可以耦合在去耦电容器的第一端子和第二端子的一个端子和第一预定电压电平和另一预定电压电平中的至少一个之间，并且可以被布置成选择性地 禁用去耦电容。

公开(公告)号：US09525294B2

公开(公告)日：2016-12-20

申请号：US15132222

申请日：2016-04-18

Applicant: MEDIATEK INC.

Inventor： Hao-Ping Hong ,  Shang-Pin Chen ,  Ding-Shiuan Shen

IPC: H02J7/00

CPC classification number: H02J7/0052 ,  G06F1/266 ,  G06F13/385 ,  G06F13/4072 ,  G06F2213/0042 ,  H02J7/0045 ,  H02J7/0068 ,  H02J7/0081 ,  H02J2007/0062

Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.

Abstract translation: 通用串行总线装置包括：具有第一引脚和第二引脚的核心电路，并具有从第一引脚和第二引脚看入核心电路的输入阻抗; 以及连接到所述核心电路的充电控制电路，被布置为选择性地将电压源提供给所述第一引脚和所述第二引脚中的一个; 其中所述核心电路的输入阻抗被配置为当所述电压源耦合到所述第一引脚和所述第二引脚中的一个引脚时使所述电压源基本上完整。

公开(公告)号：US20160233710A1

公开(公告)日：2016-08-11

申请号：US15132222

申请日：2016-04-18

Applicant: MEDIATEK INC.

Inventor： Hao-Ping Hong ,  Shang-Pin Chen ,  Ding-Shiuan Shen

IPC: H02J7/00

CPC classification number: H02J7/0052 ,  G06F1/266 ,  G06F13/385 ,  G06F13/4072 ,  G06F2213/0042 ,  H02J7/0045 ,  H02J7/0068 ,  H02J7/0081 ,  H02J2007/0062

Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.

Abstract translation: 通用串行总线装置包括：具有第一引脚和第二引脚的核心电路，并具有从第一引脚和第二引脚看入核心电路的输入阻抗; 以及连接到所述核心电路的充电控制电路，被布置为选择性地将电压源提供给所述第一引脚和所述第二引脚中的一个; 其中所述核心电路的输入阻抗被配置为当所述电压源耦合到所述第一引脚和所述第二引脚中的一个引脚时使所述电压源基本上完整。

公开(公告)号：US20150256173A1

公开(公告)日：2015-09-10

申请号：US14549552

申请日：2014-11-21

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen

IPC: H03K17/687 ,  H03K19/0948

CPC classification number: H03K17/687 ,  H03K19/018521 ,  H03K19/0948

Abstract: An apparatus for performing signal driving with aid of MOSFET and an associated IC are provided, where the apparatus includes a PMOSFET coupled between a predetermined voltage level and a terminal, and further includes an NMOSFET coupled between the predetermined voltage level and the terminal. The PMOSFET is arranged for selectively driving a signal that passes through the terminal. In addition, the NMOSFET is arranged for selectively driving the signal. Additionally, the apparatus further includes another NMOSFET coupled between another predetermined voltage level and the terminal, wherein the other NMOSFET is arranged for selectively driving the signal. More particularly, the PMOSFET, the NMOSFET, and the other NMOSFET does not drive the signal at the same time. For example, each of the PMOSFET, the NMOSFET, and the other NMOSFET selectively drives the signal to have one of a plurality of logical states.

Abstract translation: 提供了一种借助于MOSFET和相关联的IC来执行信号驱动的装置，其中装置包括耦合在预定电压电平和端子之间的PMOSFET，并且还包括耦合在预定电压电平和端子之间的NMOSFET。 PMOSFET布置用于选择性地驱动通过端子的信号。 此外，NMOSFET被布置用于选择性地驱动信号。 另外，该装置还包括耦合在另一预定电压电平和端子之间的另一个NMOSFET，其中另一个NMOSFET被布置用于选择性地驱动该信号。 更具体地，PMOSFET，NMOSFET和另一个NMOSFET不会同时驱动信号。 例如，PMOSFET，NMOSFET和其它NMOSFET中的每一个选择性地驱动信号以具有多个逻辑状态之一。