公开(公告)号：US20250046390A1

公开(公告)日：2025-02-06

申请号：US18774447

申请日：2024-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fulvio Rori ,  Pitamber Shukla ,  Chiara Cerafogli ,  Erasmo Jose B. Vargas

IPC: G11C29/12

Abstract: A methods and system directed to a wordline ramp rate monitor for early detection of defect activation are disclosed. A memory access directed to a wordline is initiated. Based on an applied ramping voltage, a ramp rate of the wordline is determined. Responsive to determining that the ramp rate satisfied a defect condition, the memory access operation is aborted.

公开(公告)号：US12087375B2

公开(公告)日：2024-09-10

申请号：US17519676

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32

CPC classification number: G11C16/3472 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3445 ,  G11C11/56

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US20240070893A1

公开(公告)日：2024-02-29

申请号：US17898079

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Maithilee Motlag ,  Hope Henry ,  Nkiruka Christian ,  Chiara Cerafogli

IPC: G06T7/70 ,  G06T1/60 ,  G06V10/44 ,  G06V10/74

CPC classification number: G06T7/70 ,  G06T1/60 ,  G06V10/44 ,  G06V10/761 ,  G06V2201/07

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with determining a location of an object are described. An object location determination can include receiving a user request associated with an object, receiving first signaling from a first image source, and receiving second signaling from a second image source. The object location determination can include writing data that is based at least in part on a combination of the user request, the first signaling, and the second signaling and determining a confidence level of identification of the object associated with the user request based on the user request, the first signaling, and the second signaling. The object location determination can include identifying output data representative of a location of the object based on the confidence level and transmitting the output data representative of the location of the object via third signaling.

公开(公告)号：US20240004787A1

公开(公告)日：2024-01-04

申请号：US17853219

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Justin Bates ,  Ryan Hrinya ,  Fulvio Rori ,  Chiara Cerafogli ,  Carmine Miccoli

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F2212/251

Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

公开(公告)号：US20230367504A1

公开(公告)日：2023-11-16

申请号：US17663139

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Carla L. Christensen ,  Iolanda Del Villano ,  Lalla Fatima Drissi ,  Anna Scalesse ,  Maddalena Calzolari

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

公开(公告)号：US11561710B2

公开(公告)日：2023-01-24

申请号：US17140600

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Chiara Cerafogli ,  Marco Domenico Tiburzi ,  Fulvio Rori

IPC: G06F3/06

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

公开(公告)号：US20230017305A1

公开(公告)日：2023-01-19

申请号：US17730325

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Mattia Cichocki ,  Vladimir Mikhalev ,  Phani Bharadwaj Vanguri ,  James Eric Davis ,  Kenneth William Marr ,  Chiara Cerafogli ,  Michael James Irwin ,  Domenico Tuzi ,  Umberto Siciliani ,  Alessandro Alilla ,  Andrea Giovanni Xotta ,  Chung-Ping Wu ,  Luigi Marchese ,  Pasquale Conenna ,  Joonwoo Nam ,  Ishani Bhatt ,  Fulvio Rori ,  Andrea D'Alessandro ,  Michele Piccardi ,  Aleksey Prozapas ,  Luigi Pilolli ,  Violante Moschiano

IPC: H01L27/02 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

公开(公告)号：US20220130476A1

公开(公告)日：2022-04-28

申请号：US17519676

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32 ,  G11C16/16

Abstract: An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

公开(公告)号：US11132247B2

公开(公告)日：2021-09-28

申请号：US16049439

申请日：2018-07-30

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli ,  Scott Anthony Stoller

IPC: G06F11/07

Abstract: Aspects of the present disclosure include accessing block data stored in a memory component including memory blocks. The block data identifies bad blocks and reusable bad blocks, the reusable bad blocks having a higher level of reliability than bad blocks. Block selection is performed to select a block based on a block address. Based on the block selection and based on the block data, a tag operation is performed by setting a latch of the selected block to a first state in which access to the selected block is disabled.

公开(公告)号：US20210124511A1

公开(公告)日：2021-04-29

申请号：US17140600

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Chiara Cerafogli ,  Marco Domenico Tiburzi ,  Fulvio Rori

IPC: G06F3/06

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.