公开(公告)号：US20230206977A1

公开(公告)日：2023-06-29

申请号：US18120133

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

CPC classification number: G11C11/2259 ,  G06F13/1694 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2255

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20220343979A1

公开(公告)日：2022-10-27

申请号：US16975619

申请日：2020-03-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

公开(公告)号：US20210233578A1

公开(公告)日：2021-07-29

申请号：US17165529

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US11074949B2

公开(公告)日：2021-07-27

申请号：US16515629

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G11C11/22 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

Abstract: Techniques herein may allow a row of a subarray in a bank of a memory device to be activated before a precharge operation has been completed for a previously opened row of memory cells in the same bank. Each subarray within the bank may be associated with a respective local latching circuit, which may be used to maintain phases at the subarray independent of subsequent commands to the same bank. For example, the latching circuit may internalize timing signals triggered by a precharge command for a first row such that if an activation command is received for a different subarray in the same bank at a time before the precharge operation of the first row is complete, the precharge operation may continue until the first row is closed, as the timing signals triggered by the precharge command may be maintained locally at the subarray using the latching circuit.

公开(公告)号：US10762944B2

公开(公告)日：2020-09-01

申请号：US15845893

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20190189177A1

公开(公告)日：2019-06-20

申请号：US15845893

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20140233338A1

公开(公告)日：2014-08-21

申请号：US14261674

申请日：2014-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C8/14

Abstract: A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

Abstract translation: 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

公开(公告)号：US12300305B2

公开(公告)日：2025-05-13

申请号：US18582185

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C8/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US12183421B2

公开(公告)日：2024-12-31

申请号：US18408228

申请日：2024-01-09

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Efrem Bolandrina

IPC: G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

公开(公告)号：US11967372B2

公开(公告)日：2024-04-23

申请号：US17655957

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C13/04 ,  G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71

Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.