公开(公告)号：US20230115339A1

公开(公告)日：2023-04-13

申请号：US17496667

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hongmei Wang ,  Hari Giduturi

IPC: G11C13/00

Abstract: Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

公开(公告)号：US20220244874A1

公开(公告)日：2022-08-04

申请号：US17163683

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F3/06

Abstract: A semiconductor device includes a memory partition. The semiconductor device further includes a plurality of registers. A first register of the plurality of registers, when in operation, controls an operation associated with the memory partition. The semiconductor device additionally includes a memory controller. When in operation, the memory controller accesses a first location of the memory partition concurrently with accessing the first register.

公开(公告)号：US20220130447A1

公开(公告)日：2022-04-28

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Embodiments relate to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. Embodiments are directed to writing and reading memory cell pairs.

公开(公告)号：US20210143732A1

公开(公告)日：2021-05-13

申请号：US17074510

申请日：2020-10-19

Applicant: Micron Technology, Inc.

Inventor： Arvind Muralidharan ,  Hari Giduturi

IPC: H02M3/07 ,  H02M1/32

Abstract: Systems and methods of memory operation involving charge pump circuitry located on a die and coupled to external pump capacitors are disclosed. In one embodiment, an exemplary system may comprise a memory die containing a memory array and charge pump circuitry configured to generate a pump voltage supplied to the memory array, and one or more pump capacitors located external to the die and configured to hold stored charge that is used to generate the pump voltage. Some embodiments may include a tank capacitor, also located off-die, to condition the charge provided from the pump capacitor. According to further embodiments, the charge pump circuitry may include one or both of max current control circuitry and/or switch resistance control circuitry that may be utilized, for example, to adjust peak current.

公开(公告)号：US10911049B2

公开(公告)日：2021-02-02

申请号：US16517000

申请日：2019-07-19

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Hari Giduturi

IPC: H03K17/10 ,  H03K19/0185 ,  H03K5/003 ,  H03K5/00

Abstract: Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.

公开(公告)号：US09870820B2

公开(公告)日：2018-01-16

申请号：US15470492

申请日：2017-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Hari Giduturi ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/50004 ,  G11C2013/009 ,  G11C2029/5004 ,  G11C2213/72 ,  G11C2213/76

Abstract: Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

公开(公告)号：US20240319879A1

公开(公告)日：2024-09-26

申请号：US18736247

申请日：2024-06-06

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi ,  Bret Addison Johnson

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: A device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. The device also includes a second bus directly coupled to the first memory die. The first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.

公开(公告)号：US20240312518A1

公开(公告)日：2024-09-19

申请号：US18586149

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/50

CPC classification number: G11C11/5642 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/5628 ,  G11C29/50004

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US11887665B2

公开(公告)日：2024-01-30

申请号：US17720542

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/73

Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.

公开(公告)号：US20230335176A1

公开(公告)日：2023-10-19

申请号：US17723740

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/4076 ,  G11C5/06 ,  H01L25/065

CPC classification number: G11C11/4076 ,  G11C5/06 ,  H01L25/0657 ,  G11C5/04

Abstract: A packaged memory device can include a primary memory die coupled to a shared intra-package communication bus and coupled to an external host device using a host interface bus, and the host interface bus can include a host clock channel. The memory device can include multiple secondary dies coupled to the intra-package communication bus, and each of the secondary dies can be configured to receive the same messages from the primary memory die using the intra-package communication bus. The primary memory die can send a first message to, or receive a first message from, a particular one of the secondary dies using the intra-package communication bus, and the first message can include a first chip identification field that exclusively indicates the particular one of the secondary dies.