公开(公告)号：US08767454B2

公开(公告)日：2014-07-01

申请号：US13673141

申请日：2012-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/16 ,  H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/329 ,  H01F41/306 ,  H01F41/307 ,  H01L27/228 ,  Y10S977/70

Abstract: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract translation: 提供包括非磁性细丝接触的磁性单元结构以及制造该结构的方法。 磁性单元结构包括自由层，钉扎层，自由层和被钉扎层之间的绝缘层，以及绝缘层中的非磁性细丝接触，其电连接自由层和被钉扎层。 非磁性细丝接触由非磁性源层形成，也在自由层和被钉扎层之间。 灯丝接触引导编程电流通过磁性电池结构，使得自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

公开(公告)号：US20140146596A1

公开(公告)日：2014-05-29

申请号：US14171239

申请日：2014-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

Abstract: Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed resistance value, to adjust a programming parameter value of the signal if the programmed resistance value is outside a target resistance value range, and to repeat at least one of the programming and the adjusting if the programmed resistance value is outside the target resistance value range, the signal including a different programming parameter value each time the programming is repeated.

Abstract translation: 一些实施例包括具有模块的方法和装置，其被配置为使用信号对存储器单元进行编程以使存储器单元具有编程的电阻值，以便如果编程的电阻值在目标电阻值之外，则调整该信号的编程参数值 并且如果编程的电阻值在目标电阻值范围之外，则重复编程和调整中的至少一个，该信号在每次重复编程时包括不同的编程参数值。

公开(公告)号：US08735216B2

公开(公告)日：2014-05-27

申请号：US13763664

申请日：2013-02-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Jian Li

IPC: H01L21/06

CPC classification number: H01L45/1608 ,  H01L21/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract translation: 一些实施例包括用于制造存储器单元结构的方法。 存储单元可以形成为具有可编程材料，以直接抵抗具有与可编程材料不同的膨胀系数的材料。 可以在可编程材料附近形成保持壳。 可以对存储单元进行热处理以将存储单元的温度升高至至少约300℃，从而在存储单元内引起热诱导的应力。 保持壳可以提供基本上平衡热诱导应力的应力。 一些实施例包括存储器单元结构。 这些结构可以包括直接针对氮化硅的可编程材料，其具有小于或等于约200兆帕的内部应力。 该结构还可以包括具有至少约500兆帕的内应力的保持壳氮化硅。

公开(公告)号：US08729520B2

公开(公告)日：2014-05-20

申请号：US13888674

申请日：2013-05-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L21/02225 ,  H01L27/2409 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract translation: 一种方法包括在具有含金属的导电互连的集成电路上形成电绝缘体材料，并激活衬底的半导体材料中的掺杂剂以提供掺杂区域。 掺杂区域提供相反导电类型的结。 在激活掺杂剂之后，衬底被结合到绝缘体材料上，并且至少部分衬底在与绝缘体材料接合的情况下被去除。 在移除之后，形成具有字线，存取二极管，含有硫族化物相变材料的状态可变存储元件和全部电连接的位线的存储单元，该存储二极管包含该结作为pn结 。 存储器件包括绝缘体材料上的粘合材料并将字线连接到绝缘体材料上。

公开(公告)号：US20130170291A1

公开(公告)日：2013-07-04

申请号：US13776354

申请日：2013-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu

IPC: H01L45/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4097 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract translation: 可变电阻存储器阵列，编程可变电阻存储元件和形成阵列的方法。 可变电阻存储器阵列形成有围绕每个相变存储元件的多个字线晶体管。 为了对所选择的可变电阻存储元件进行编程，所有位线都以相同的电压接地或偏置。 选择与所选择的可变电阻存储元件接触的顶部电极选择线。 具有围绕所选择的可变电阻存储元件的字线晶体管的字线被接通以向该元件提供编程电流。 电流从所选择的顶部电极选择线通过可变电阻存储元件流入周围字线晶体管的公共源极/漏极区域，跨越晶体管到最近的位线触点。 字线被图案化成各种格子构型。

公开(公告)号：US20130157410A1

公开(公告)日：2013-06-20

申请号：US13763664

申请日：2013-02-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Jian Li

IPC: H01L21/06

CPC classification number: H01L45/1608 ,  H01L21/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract translation: 一些实施例包括用于制造存储器单元结构的方法。 存储单元可以形成为具有可编程材料，以直接抵抗具有与可编程材料不同的膨胀系数的材料。 可以在可编程材料附近形成保持壳。 可以对存储单元进行热处理以将存储单元的温度升高至至少约300℃，从而在存储单元内引起热诱导的应力。 保持壳可以提供基本上平衡热诱导应力的应力。 一些实施例包括存储器单元结构。 这些结构可以包括直接针对氮化硅的可编程材料，其具有小于或等于约200兆帕的内部应力。 该结构还可以包括具有至少约500兆帕的内应力的保持壳氮化硅。

公开(公告)号：US20130064011A1

公开(公告)日：2013-03-14

申请号：US13673130

申请日：2012-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Steve Kramer ,  Gurtej Sandhu

IPC: G11C11/16 ,  H01L21/8246 ,  G11C11/14 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C11/16 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

Abstract translation: 提供了包括压电材料的磁存储单元和操作存储单元的方法。 存储单元包括堆叠，并且压电材料可以形成为堆叠中的层或邻近电池堆的层。 压电材料可以用于在编程存储器单元期间引起瞬态应力以减小存储器单元的关键开关电流。

公开(公告)号：US20130064010A1

公开(公告)日：2013-03-14

申请号：US13673141

申请日：2012-11-09

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/16 ,  H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/08 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/329 ,  H01F41/306 ,  H01F41/307 ,  H01L27/228 ,  Y10S977/70

Abstract: A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract translation: 提供包括非磁性细丝接触的磁性单元结构以及制造该结构的方法。 磁性单元结构包括自由层，钉扎层，自由层和被钉扎层之间的绝缘层，以及绝缘层中的非磁性细丝接触，其电连接自由层和被钉扎层。 非磁性细丝接触由非磁性源层形成，也在自由层和被钉扎层之间。 灯丝接触引导编程电流通过磁性电池结构，使得自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

公开(公告)号：US10991759B2

公开(公告)日：2021-04-27

申请号：US15497032

申请日：2017-04-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Sanh D. Tang ,  David H. Wells

IPC: H01L27/24 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78 ,  H01L45/00 ,  H01L21/8234 ,  H01L29/45

Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

公开(公告)号：US10573366B2

公开(公告)日：2020-02-25

申请号：US16164606

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej Sandhu

IPC: G11C11/16 ,  H01L43/02

Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.