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    Semiconductor device structures
    31.
    发明授权
    Semiconductor device structures 有权

    公开(公告)号：US10032719B2

    公开(公告)日：2018-07-24

    申请号：US15606312

    申请日：2017-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue (Gloria) Chen ,  Anton J. deVilliers

    IPC: H01L21/31 ,  H01L23/528 ,  H01L21/02 ,  H01L21/027 ,  H01L23/52 ,  H01L21/768 ,  H01L21/308 ,  H01L21/467

    Abstract: A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

    SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE LINES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES
    34.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE LINES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES 有权
    包括导电线的半导体器件和形成半导体器件的方法

    公开(公告)号：US20170062324A1

    公开(公告)日：2017-03-02

    申请号：US14838768

    申请日：2015-08-28

    Applicant: Micron Technology, Inc.

    Inventor： William R. Brown ,  Jenna L. Russon ,  Tim H. Bossart ,  Brian R. Watson ,  Nikolay A. Mirin ,  David A. Kewley

    IPC: H01L23/528 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5283 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11582 ,  H01L28/00

    Abstract: A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

    Abstract translation: 公开了一种包括导线的半导体器件。 第一导电线各自包括第一部分，第二部分和扩大部分，所述扩大部分连接第一导电线的第一部分和第二部分。 半导体器件包括第二导线，至少一些第二导线设置在一对第一导线之间，每个第二导线在第二导线的端部处包括比在其它部分的截面积更大的截面积 其中。 所述半导体器件包括在所述第一导线和所述第二导线中的每一个上的焊盘，其中，所述第二导线中的每一个上的所述焊盘位于所述第二导线的端部上， 部分。

    Methods of processing semiconductor substrates in forming scribe line alignment marks
    38.
    发明授权
    Methods of processing semiconductor substrates in forming scribe line alignment marks 有权
    在形成划线对准标记时处理半导体衬底的方法

    公开(公告)号：US08956976B2

    公开(公告)日：2015-02-17

    申请号：US14171848

    申请日：2014-02-04

    Applicant: Micron Technology, Inc.

    Inventor： William R. Brown ,  David Kewley ,  Adam Olson

    IPC: H01L21/302 ,  H01L21/308 ,  G03F9/00 ,  H01L21/033

    CPC classification number: H01L21/308 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0337 ,  H01L21/3086

    Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning.

    Abstract translation: 在形成划线对准标记中处理半导体衬底的方法包括在半导体衬底的划线区域内形成间距倍数非电路特征。 在横截面中，特征的个体具有小于在光刻图案化基底中使用的最小光刻特征尺寸的最大宽度。 光刻胶沉积在特征上。 将其图案化以形成在横截面中单独地接收在相应的一对特征之间的光致抗蚀剂块。 各对的特征的个体在横截面中具有横向最内侧的侧壁。 光致抗蚀剂块的个体在横截面中具有相对的一对第一图案边缘，其横向相对于相应的一对特征的横向最内侧的内侧间隔开。 光致抗蚀剂块的个体在横截面中具有相对的一对第二图案边缘，其在图案化期间自动对准第一图案边缘的横向外侧到特征的侧向最内侧。

    Methods of forming features in semiconductor device structures
    39.
    发明授权
    Methods of forming features in semiconductor device structures 有权
    在半导体器件结构中形成特征的方法

    公开(公告)号：US08815752B2

    公开(公告)日：2014-08-26

    申请号：US13687419

    申请日：2012-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Adam L. Olson ,  Kaveri Jain ,  Lijing Gou ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Anton J. deVilliers

    IPC: H01L21/31 ,  H01L21/469

    CPC classification number: H01L23/528 ,  H01L21/0226 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/441 ,  H01L21/467 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed.

    Abstract translation: 公开了形成特征的方法。 一种方法包括在衬底结构上的酸性或碱性材料池上形成抗蚀剂，选择性地将抗蚀剂暴露于能量源以形成暴露的抗蚀剂部分和未曝光的抗蚀剂部分，以及将酸性或碱性材料的酸或碱扩散 从池中到抗蚀剂的近端部分。 另一种方法包括在衬底结构中形成多个凹陷。 多个凹部填充有包含酸或碱的池材料。 在池材料上形成抗蚀剂，并且衬底结构和酸或碱扩散到抗蚀剂的相邻部分。 抗蚀剂被图案化以在抗蚀剂中形成开口。 开口包括远离衬底结构的较宽部分和靠近衬底结构的较窄部分。 公开了包括这些特征的附加方法和半导体器件结构。

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