公开(公告)号：US08574987B1

公开(公告)日：2013-11-05

申请号：US13491760

申请日：2012-06-08

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/823456 ,  H01L27/11534 ,  H01L29/66545

摘要： A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.

摘要翻译： 在NVM区域和逻辑区域中的半导体层上形成第一介电层。 在NVM和逻辑区域中的第一介电层上形成电荷存储层。 对电荷存储层进行图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。 在NVM的半导体层上形成第二电介质层，围绕电荷存储结构和虚拟栅极的逻辑区域形成。 虚拟门被一个逻辑门代替。 从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。 在电荷存储结构上形成第三电介质层，并且在第三介电层上形成控制栅层。

公开(公告)号：US08389365B2

公开(公告)日：2013-03-05

申请号：US13077501

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11536 ,  H01L29/66825

摘要： A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.

摘要翻译： 公开了一种用于形成用于非易失性存储单元晶体管的集成电路的方法，其包括：在所述衬底的第一区域和所述衬底的第二区域中的衬底上形成离散存储元件层; 在所述第一区域和所述第二区域中的离散存储元件层上形成第一介电材料层; 在所述第一区域和所述第二区域中的所述第一介电材料层上形成阻挡功函数材料的第一层; 以及从所述第二区域去除所述第一层屏障功能材料，从所述第二区域去除所述第一介电材料层，以及从所述第二区域移除所述离散存储元件层。 在去除之后，在第一区域和第二区域中的衬底上形成第二层屏障功能材料层。 从第一区域去除第二层屏障功能材料。 存储器件的第一栅极形成在第一区域中。 第一栅极包括第一层屏障功能材料的一部分。 存储器件包括电荷存储结构，其包括离散存储元件层的一部分。 晶体管的第二栅极形成在第二区域中，第二栅极包括第二层屏障功能材料的一部分。

公开(公告)号：US08318576B2

公开(公告)日：2012-11-27

申请号：US13092046

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L27/0629 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.

摘要翻译： 一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板 通过STI区域并且通过侧壁电介质层与串扰隔离。

公开(公告)号：US20120267759A1

公开(公告)日：2012-10-25

申请号：US13092046

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L27/0629 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.

摘要翻译： 一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板 通过STI区域并且通过侧壁电介质层与串扰隔离。

公开(公告)号：US20120267758A1

公开(公告)日：2012-10-25

申请号：US13092037

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).

摘要翻译： 半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层（10）中的底部电容器板，电容器电介质层（22）和凹陷 顶部电容器板（28），其被STI区域（30）覆盖并且由侧壁电介质层（23）与串扰隔离。

公开(公告)号：US09702925B2

公开(公告)日：2017-07-11

申请号：US14514449

申请日：2014-10-15

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Steven G. H. Anderson ,  Mehul D. Shroff

IPC分类号： G01R31/26 ,  H01L27/06 ,  G01R31/3181

CPC分类号： G01R31/2632 ,  G01R31/2644 ,  G01R31/31816 ,  H01L27/0629

摘要： A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

公开(公告)号：US09252152B2

公开(公告)日：2016-02-02

申请号：US14228678

申请日：2014-03-28

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/338 ,  H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3105

CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

公开(公告)号：US09231077B2

公开(公告)日：2016-01-05

申请号：US14195299

申请日：2014-03-03

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3213

CPC分类号： H01L29/66484 ,  H01L21/28273 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833

摘要： A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

摘要翻译： 形成半导体器件的方法包括在NVM区域和逻辑区域中的衬底上形成第一栅极层; 在NVM区域中的第一栅极层中形成开口; 在开口中形成电荷存储层; 在开口中的电荷存储层上形成控制栅极; 图案化第一栅极层以在逻辑区域中的衬底上形成第一图案化栅极层部分，并且在NVM区域中的衬底上形成第二图案化栅极层部分，其中第二图案化栅极层部分与控制栅极相邻; 在所述第一图案化栅极层部分周围以及所述第二图案化栅极层部分和所述控制栅极周围的所述基板上方形成介电层，并用包含金属的逻辑门代替所述第一图案化栅极层部分。

公开(公告)号：US20130171785A1

公开(公告)日：2013-07-04

申请号：US13343331

申请日：2012-01-04

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8239

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在高k电介质上，如逻辑晶体管的金属逻辑门。 在形成NVM单元的金属选择栅极的同时形成逻辑晶体管，包括形成源极/漏极。 逻辑晶体管被保护，同时形成NVM单元，包括在金属选择栅极的一部分和衬底上的电荷存储区域的一部分上使用金属纳米晶体和金属控制栅极形成电荷存储区域。 蚀刻电荷存储区域以与金属控制栅极对准。

公开(公告)号：US08318577B2

公开(公告)日：2012-11-27

申请号：US13096528

申请日：2011-04-28

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/20

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： Forming a capacitor structure includes forming a first dielectric layer over a conductive region, wherein the first dielectric layer has a first conductive layer at a top surface of the first dielectric layer; forming a first opening in the first dielectric layer over the conductive region, wherein the first opening exposes a first sidewall of the first conductive layer; forming a second conductive layer within the first opening, wherein the second conductive layer contacts the first sidewall of the first conductive layer; removing a portion of the second conductive layer from the bottom of the first opening; forming an insulating layer within the first opening; removing a portion of the insulating layer from the bottom of the first opening; extending the first opening through the first dielectric layer to expose the conductive region; and filling the first opening with a conductive material, wherein the conductive material contacts the conductive region.

摘要翻译： 形成电容器结构包括在导电区域上形成第一电介质层，其中第一介电层在第一电介质层的顶表面具有第一导电层; 在所述导电区域上在所述第一电介质层中形成第一开口，其中所述第一开口暴露所述第一导电层的第一侧壁; 在所述第一开口内形成第二导电层，其中所述第二导电层接触所述第一导电层的第一侧壁; 从所述第一开口的底部移除所述第二导电层的一部分; 在所述第一开口内形成绝缘层; 从所述第一开口的底部去除绝缘层的一部分; 将第一开口延伸穿过第一介电层以暴露导电区域; 以及用导电材料填充所述第一开口，其中所述导电材料接触所述导电区域。