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116 条记录 (耗时 0.028 秒)

    Method of manufacturing a semiconductor memory with deuterated materials
    32.
    发明授权
    Method of manufacturing a semiconductor memory with deuterated materials 有权
    用氘代材料制造半导体存储器的方法

    公开(公告)号：US06884681B1

    公开(公告)日：2005-04-26

    申请号：US10672093

    申请日：2003-09-26

    申请人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    发明人： Tazrien Kamal ,  Arvind Halliyal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Rinji Sugino

    IPC分类号： H01L21/336 ,  H01L21/8246

    CPC分类号： H01L27/11568 ,  H01L29/66833

    摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.

    摘要翻译： 一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。 植入第一和第二位线，并在完成内存之前形成字线。 在字线之间形成间隔，并且在字线之间形成层间电介质层。 第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

    Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation
    33.
    发明授权
    Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer dielectric formation 有权
    在层间电介质形成中使用ARC层时降低电荷增益和电荷损失的方法和系统

    公开(公告)号：US06727143B1

    公开(公告)日：2004-04-27

    申请号：US09533619

    申请日：2000-03-22

    申请人： Angela T. Hui ,  Mark T. Ramsbey ,  Yu Sun ,  David H. Matsumoto

    发明人： Angela T. Hui ,  Mark T. Ramsbey ,  Yu Sun ,  David H. Matsumoto

    IPC分类号： H01L218242

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The method and system further include providing an antireflective coating (ARC) layer. At least a portion of the ARC layer is on the interlayer dielectric. The method and system further include providing a plurality of via holes in the interlayer dielectric and the ARC layer and filling the plurality of via holes with a conductive material. The method and system further include removing the ARC layer while reducing subsequent undesirable charge gain and subsequent undesirable charge loss over the use of a chemical mechanical polish in removing the ARC layer.

    摘要翻译： 公开了一种用于将半导体器件的下层与半导体器件的上层绝缘的方法和系统。 该方法和系统包括在下层上提供层间电介质。 该方法和系统还包括提供抗反射涂层（ARC）层。 ARC层的至少一部分在层间电介质上。 该方法和系统还包括在层间电介质和ARC层中提供多个通孔，并用导电材料填充多个通孔。 该方法和系统还包括去除ARC层，同时减少随后的不期望的电荷增益和随后的不期望的电荷损失，使用化学机械抛光剂去除ARC层。

    Dummy wordline for erase and bitline leakage
    34.
    发明授权
    Dummy wordline for erase and bitline leakage 有权
    用于擦除和位线泄漏的虚拟字线

    公开(公告)号：US06707078B1

    公开(公告)日：2004-03-16

    申请号：US10230729

    申请日：2002-08-29

    申请人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    发明人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    IPC分类号： H01L2968

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L27/115

    摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

    摘要翻译： 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

    Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
    36.
    发明授权
    Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 失效
    用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法

    公开(公告)号：US06639271B1

    公开(公告)日：2003-10-28

    申请号：US10027253

    申请日：2001-12-20

    申请人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

    发明人： Wei Zheng ,  Mark W. Randolph ,  Nicholas H. Tripsas ,  Zoran Krivokapic ,  Jack F. Thomas ,  Mark T. Ramsbey

    IPC分类号： H01L29792

    CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

    摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

    摘要翻译： 在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。 该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层 势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。 去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

    Method of making memory wordline hard mask extension
    39.
    发明授权
    Method of making memory wordline hard mask extension 有权
    制作内存字线硬掩模扩展的方法

    公开(公告)号：US06479348B1

    公开(公告)日：2002-11-12

    申请号：US10109516

    申请日：2002-08-27

    申请人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

    发明人： Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Hidehiko Shiraiwa ,  Angela T. Hui

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.

    摘要翻译： 提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。 在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。 字线材料和硬掩模材料沉积在字线材料上。 光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。 使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。 使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

    Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory
    40.
    发明授权
    Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
    制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法

    公开(公告)号：US06465303B1

    公开(公告)日：2002-10-15

    申请号：US09885490

    申请日：2001-06-20

    申请人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

    发明人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

    摘要翻译： 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。